Abstract: A system and method for efficient power management of an integrated circuit are described. In various implementations, a computing system includes an integrated circuit, multiple voltage regulators, and circuitry that detects when current drawn from a power rail from one of the multiple voltage regulators exceeds a limit. Upon detection, a single global alarm signal is asserted and conveyed to the integrate circuit. The integrated circuit includes at least a first group of functional blocks sharing a first power rail and a second group of functional blocks sharing a second power rail. When the global alarm signal is asserted, the functional blocks of the first group and the second group perform steps to immediately reduce power consumption. In order to maintain performance and satisfy a quality of service (QoS) parameter, a power management controller of the integrated circuit reassigns power limits shortly thereafter.

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.