Patents by Inventor Michael MacDougal
Michael MacDougal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11676976Abstract: A PIN photodetector includes an n-type semiconductor layer, an n-type semiconductor cap layer, a first plurality of p-type regions located within the n-type semiconductor cap layer and separated from one another by a distance d1, and an absorber layer located between the n-type semiconductor layer and the n-type semiconductor cap layer including the first plurality of p-type regions. The plurality of p-type regions are electrically connected to one another to provide an electrical response to light incident to the PIN photodetector.Type: GrantFiled: November 2, 2020Date of Patent: June 13, 2023Assignee: Attollo Engineering, LLCInventors: Jonathan Geske, Andrew Hood, Michael MacDougal
-
Patent number: 11495562Abstract: A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.Type: GrantFiled: December 27, 2019Date of Patent: November 8, 2022Assignee: Attollo Engineering, LLCInventors: Michael MacDougal, Andrew Hood
-
Publication number: 20210202420Abstract: A hybridized image sensor includes a first die and a second die. The first die includes a first surface, a first plurality of conductive bumps fabricated on the first surface, and a first alignment feature fabricated on the first surface. The second die includes a second surface, a second plurality of conductive bumps fabricated on the second surface, and second alignment features fabricated on the second surface, wherein the first alignment features interact with the second alignment features to align the first plurality of conductive bumps with the second plurality of conductive bumps.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: Michael MacDougal, Andrew Hood
-
Publication number: 20210082973Abstract: A PIN photodetector includes an n-type semiconductor layer, an n-type semiconductor cap layer, a first plurality of p-type regions located within the n-type semiconductor cap layer and separated from one another by a distance d1, and an absorber layer located between the n-type semiconductor layer and the n-type semiconductor cap layer including the first plurality of p-type regions. The plurality of p-type regions are electrically connected to one another to provide an electrical response to light incident to the PIN photodetector.Type: ApplicationFiled: November 2, 2020Publication date: March 18, 2021Inventors: Jonathan Geske, Andrew Hood, Michael MacDougal
-
Patent number: 10854646Abstract: A PIN photodetector includes an n-type semiconductor layer, an n-type semiconductor cap layer, a first plurality of p-type regions located within the n-type semiconductor cap layer and separated from one another by a distance d1, and an absorber layer located between the n-type semiconductor layer and the n-type semiconductor cap layer including the first plurality of p-type regions. The plurality of p-type regions are electrically connected to one another to provide an electrical response to light incident to the PIN photodetector.Type: GrantFiled: October 19, 2018Date of Patent: December 1, 2020Assignee: ATTOLLO ENGINEERING, LLCInventors: Jonathan Geske, Andrew Hood, Michael MacDougal
-
Publication number: 20200127023Abstract: A PIN photodetector includes an n-type semiconductor layer, an n-type semiconductor cap layer, a first plurality of p-type regions located within the n-type semiconductor cap layer and separated from one another by a distance d1, and an absorber layer located between the n-type semiconductor layer and the n-type semiconductor cap layer including the first plurality of p-type regions. The plurality of p-type regions are electrically connected to one another to provide an electrical response to light incident to the PIN photodetector.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Jonathan Geske, Andrew Hood, Michael MacDougal
-
Patent number: 8654811Abstract: Vertical Cavity Surface Emitting Laser (VCSEL) arrays with vias for electrical connection are disclosed. A Vertical Cavity Surface Emitting Laser (VCSEL) array in accordance with one or more embodiments of the present invention comprises a plurality of first mirrors, a plurality of second mirrors, a plurality of active regions, coupled between the plurality of first mirrors and the plurality of second mirrors, and a heatsink, thermally and mechanically coupled to the second mirror opposite the plurality of active regions, wherein an electrical path to at least one of the plurality of second mirrors is made through a via formed through a depth of the plurality of second mirrors, and a plurality of VCSELs in the VCSEL array are connected in series.Type: GrantFiled: August 25, 2010Date of Patent: February 18, 2014Assignee: Flir Systems, Inc.Inventors: Jonathan C. Geske, Chad Shin-deh Wang, Michael MacDougal
-
Patent number: 8581168Abstract: A single camera capable of capturing high speed laser return pulses for a target, as well as provide imaging information on the background of the target. This capability is enabled by having a read-out integrated circuit (ROIC) capable of extracting both types of information from a pixel of a focal plane array (FPA). Further, an ROIC topology that allows for the ability to distinguish between high frequency and low frequency signal paths, and provide supporting circuitry to process the two paths separately. One path may integrate the low frequency background scene to provide a high fidelity image of the scene. The second path may process high frequency noise and multiple laser pulse returns within a frame. These two paths may be combined to provide a background image with a superimposed laser return.Type: GrantFiled: March 29, 2011Date of Patent: November 12, 2013Assignee: Flir Systems, Inc.Inventors: Lloyd F. Linder, Daniel Renner, Michael MacDougal, Jonathan Geske, R. Jacob Baker
-
Patent number: 8324659Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.Type: GrantFiled: March 24, 2011Date of Patent: December 4, 2012Assignee: Aerius Photonics LLCInventors: Michael MacDougal, Jonathan Geske, John E. Bowers
-
Publication number: 20120248288Abstract: Embodiments of the invention describe solutions directed towards having a single camera capable of capturing high speed laser return pulses for a target, as well as provide imaging information on the background of the target. This capability is enabled by having a read-out integrated circuit (ROIC) capable of extracting both types of information from a pixel of a focal plane array (FPA). Embodiments of the invention describe an ROIC topology that allows for the ability to distinguish between high frequency and low frequency signal paths, and provide supporting circuitry to process the two paths separately. One path may integrate the low frequency background scene to provide a high fidelity image of the scene. The second path may process high frequency noise and multiple laser pulse returns within a frame. These two paths may be combined to provide a background image with a superimposed laser return.Type: ApplicationFiled: March 29, 2011Publication date: October 4, 2012Inventors: Lloyd F. Linder, Daniel Renner, Michael MacDougal, Jonathan Geske, R. Jacob Baker
-
Publication number: 20120051384Abstract: Vertical Cavity Surface Emitting Laser (VCSEL) arrays with vias for electrical connection are disclosed. A Vertical Cavity Surface Emitting Laser (VCSEL) array in accordance with one or more embodiments of the present invention comprises a plurality of first mirrors, a plurality of second mirrors, a plurality of active regions, coupled between the plurality of first mirrors and the plurality of second mirrors, and a heatsink, thermally and mechanically coupled to the second mirror opposite the plurality of active regions, wherein an electrical path to at least one of the plurality of second mirrors is made through a via formed through a depth of the plurality of second mirrors, and a plurality of VCSELs in the VCSEL array are connected in series.Type: ApplicationFiled: August 25, 2010Publication date: March 1, 2012Applicant: AERIUS PHOTONICS, LLCInventors: Jonathan C. Geske, Chad Shin-deh Wang, Michael MacDougal
-
Publication number: 20110169048Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.Type: ApplicationFiled: March 24, 2011Publication date: July 14, 2011Applicant: AERIUS PHOTONICS LLCInventors: Michael MacDougal, Jonathan Geske, John E. Bowers
-
Patent number: 7915639Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.Type: GrantFiled: October 20, 2008Date of Patent: March 29, 2011Assignee: Aerius Photonics LLCInventors: Michael MacDougal, Jonathan Geske, John E. Bowers
-
Publication number: 20100096665Abstract: Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: AERIUS PHOTONICS LLCInventors: Michael MacDougal, Jonathan Geske, John E. Bowers