Abstract: A differential input driver circuit (10, 50) includes first and second transistors (Q0, Q3) as input transistors and third and fourth transistors (Q1, Q2) as diode-connected, cross-coupled transistors. In one embodiment, first, second, third and fourth transistors are NPN bipolar transistors. The base terminals of the first and third transistors are connected while the base terminals of the second and fourth transistors are connected. The input transistors receive a pair of differential input signals (In+/?) at the emitter terminals (24, 26) and provides a pair of differential output signals (Vo+/?) at the collector terminals (16, 18). The emitter terminals of the diode-connected transistors (Q1, Q2) couple the input signal at the emitter terminal of the first transistor to the collector terminal of the second transistor and vice versa. The cross-coupling of the third and fourth transistors enables the input driver to operate effectively in single-ended to differential conversion mode.

Abstract: A differential input driver circuit (10, 50) includes first and second transistors (Q0, Q3) as input transistors and third and fourth transistors (Q1, Q2) as diode-connected, cross-coupled transistors. In one embodiment, first, second, third and fourth transistors are NPN bipolar transistors. The base terminals of the first and third transistors are connected while the base terminals of the second and fourth transistors are connected. The input transistors receive a pair of differential input signals (In+/?) at the emitter terminals (24, 26) and provides a pair of differential output signals (Vo+/?) at the collector terminals (16, 18). The emitter terminals of the diode-connected transistors (Q1, Q2) couple the input signal at the emitter terminal of the first transistor to the collector terminal of the second transistor and vice versa. The cross-coupling of the third and fourth transistors enables the input driver to operate effectively in single-ended to differential conversion mode.

Abstract: An amplifier circuit which operates to level shift a differential input signal and to provide a single-ended output. The circuit includes a level shifting stage which defines two current paths, with one path being controlled by one component of the differential input and the other path being controlled by the other component. A transistor is connected in series with each of the current paths. A driver stage coupled to the first and second current paths provides first and second driver outputs indicative of voltage levels on the first and second current paths. A common mode feedback circuit operates to alter current flow in the current paths in response to the first and second driver outputs. An output stage includes one output transistor coupled between one power supply rail and an amplifier output and another transistor output transistor coupled between a second power supply rail and the amplifier output.

Abstract: A transistor saturation control circuit for controlling saturation of a PNP transistor. The control circuit includes current sense circuitry which produces a control output in response to a change in current of an N well associated with the PNP transistor. Base drive control circuitry operates to limit base drive to the PNP transistor in response to the control output.

Abstract: An amplifier output stage including a PNP transistor having an emitter coupled to a power rail and a collector coupled to an amplifier output. The PNP transistor is driven by an NPN transistor having a collector coupled to the base of the PNP transistor. A bias circuit produces a base-emitter voltage across the PNP transistor so that the PNP transistor will conduct a desired quiescent current. The bias circuit has an effective output impedance which is sufficiently large to form a pole in combination with a frequency compensation capacitor coupled to the collector of the PNP transistor, with the pole being located at a frequency beyond the unity-gain frequency of the amplifier.