Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Abstract: A method for making a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer, and a semiconductor device with integrated CMOS circuitry and RF circuitry fabricated over a semiconductor wafer is provided. The method includes forming a lower metallization layer and a lower dielectric layer over the lower metallization layer. A metallization line is formed over the lower dielectric layer with an upper dielectric layer over the metallization line. An upper metallization layer is then formed over the upper dielectric layer. After this is completed, oxide spacers are formed along the sides of the lower dielectric layer, the metallization line, and the upper dielectric layer. Finally, an encapsulating metallization layer is formed over the oxide spacers such that the lower metallization layer, the upper metallization layer and the encapsulating metallization layer define an outer shield and the metallization line defines an inner conductor of an RF line.

Abstract: A waveguide structure and method of making a waveguide for communicating optical signals is provided. The waveguide structure is made using standard CMOS fabrication operations and is integrated on the same chip having digital CMOS circuitry. An example method of making the waveguide includes forming a contact through a dielectric layer down to a substrate and coating sidewalls of the contact with a first metallization coating. The contact is then filled with a dielectric material. A partial waveguide structure is formed over the first metallization coating and the dielectric material of the contact. The partial waveguide structure is defined by a waveguide dielectric structure and a second metallization coating that is defined over the waveguide dielectric structure. A third metallization coating is then formed to define spacers along sides of the partial waveguide structure, the first metallization coating, the second metallization coating.

Abstract: The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.