Abstract: A system and method for determining cell congestion in an integrated circuit (IC) floor-plan comprising a set of rows configured for placement of components represented as cells, comprises dividing the floor-plan into a plurality of windows, selecting a window from the plurality of windows, the window comprising a subset of rows from the set of rows, for the subset of rows, determining a cell distribution comprising a number of cells in the subset of rows and determining a pin distribution for each cell in the cell distribution and determining a congestion value for the selected window as a function of the cell distribution and pin distribution.

Abstract: The uppermost metal layer (metal-one) on a flip-chip packageable IC is modified to include at least one VCC pad, at least one ground pad, and at least one and preferably five test pads. Each pad is sized to be probe wafer-contactable, is and electrically coupled to appropriate vias formed in the IC. During IC fabrication but before the destination layer is fabricated, the IC is tested using a wafer probe that couples appropriate signals and power to the pads formed on the metal-one layer. If testing discloses a bug, it is possible to modify the IC metal-one traces, e.g., using FIB and then re-wafer probe test the IC. An insulating layer and destination layer may then be fabricated over what is known to be a good IC, and re-testing may occur. In this fashion, debugging diagnostics are made using testable ICs, and any metal-one revision may be tried and confirmed before changing the metal-one pattern for mass produced ICs.