Patents by Inventor Michael Nelhiebel
Michael Nelhiebel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230194595Abstract: A circuit includes a power transistor having a main current path between a first supply node and an output pin for connecting a load. A resistance formed by a chip metallization is arranged between the main current path of the power transistor and the output pin. The circuit includes a current measuring circuit coupled to the power transistor and including a sense transistor coupled to the power transistor. The current measuring circuit delivers a measurement current representing a load current flowing through the power transistor. An amplifier circuit generates an amplifier output signal representing the voltage across the resistance, and a control circuit outputs a signal representing the measurement current in a first mode and a signal dependent on the amplifier output signal in a second mode.Type: ApplicationFiled: December 2, 2022Publication date: June 22, 2023Inventors: Christian Djelassi-Tscheck, Cristian Mihai Boianceanu, Michael Nelhiebel
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Patent number: 11443990Abstract: In some examples, a device includes a power structure and a sensing structure that is electrically isolated from the power structure. The device also includes processing circuitry configured to determine whether the sensing structure includes a prognostic health indicator, wherein the prognostic health indicator is indicative of a health of the power structure.Type: GrantFiled: June 29, 2020Date of Patent: September 13, 2022Assignee: Infineon Technologies AGInventors: Sergio De Gasperi, Michael Nelhiebel, Alexander Mayer, Dieter Haerle, Andrea Baschirotto
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Patent number: 11276624Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.Type: GrantFiled: December 17, 2019Date of Patent: March 15, 2022Assignee: Infineon Technologies Austria AGInventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
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Publication number: 20210407870Abstract: In some examples, a device includes a power structure and a sensing structure that is electrically isolated from the power structure. The device also includes processing circuitry configured to determine whether the sensing structure includes a prognostic health indicator, wherein the prognostic health indicator is indicative of a health of the power structure.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Sergio De Gasperi, Michael Nelhiebel, Alexander Mayer, Dieter Haerle, Andrea Baschirotto
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Patent number: 11171049Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.Type: GrantFiled: May 7, 2019Date of Patent: November 9, 2021Assignee: Infineon Technologies AGInventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
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Patent number: 11127693Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.Type: GrantFiled: December 11, 2019Date of Patent: September 21, 2021Assignee: Infineon Technologies AGInventors: Johann Gatterbauer, Katrin Albers, Joerg Busch, Klaus Goller, Norbert Mais, Marianne Kolitsch, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
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Publication number: 20210183732Abstract: A semiconductor device includes: a semiconductor substrate; a power device formed in the semiconductor substrate; a metal bilayer formed over the semiconductor substrate, the metal bilayer including a discontinuous metal layer formed on and in contact with a continuous base metal layer; and one or more contact pads formed in the metal bilayer or in a metallization layer above the metal bilayer. The discontinuous metal layer includes a plurality of metal blocks which are laterally spaced apart from one another and which form a heat sink structure over the power device. The continuous base metal layer is configured to laterally spread heat energy from the power device to the plurality of metal blocks. Methods of producing the semiconductor device are also described.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Inventors: Michael Nelhiebel, Heiko Assmann, Olaf Heitzsch, Jakob Kriz, Sven Lanzerstorfer, Rainer Pelzer, Werner Robl, Bernhard Weidgans, Johannes Zechner
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Patent number: 10978395Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.Type: GrantFiled: June 30, 2020Date of Patent: April 13, 2021Assignee: Infineon Technologies Austria AGInventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Bürke, Sven Schmidbauer, Michael Nelhiebel
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Patent number: 10937720Abstract: A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.Type: GrantFiled: March 28, 2019Date of Patent: March 2, 2021Assignee: Infineon Technologies Austria AGInventors: Silvia Larisegger, Michael Nelhiebel, Sabine Reither
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Publication number: 20200335448Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.Type: ApplicationFiled: June 30, 2020Publication date: October 22, 2020Inventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Bürke, Sven Schmidbauer, Michael Nelhiebel
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Patent number: 10734320Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.Type: GrantFiled: July 30, 2018Date of Patent: August 4, 2020Assignee: Infineon Technologies Austria AGInventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Buerke, Sven Schmidbauer, Michael Nelhiebel
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Patent number: 10700019Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.Type: GrantFiled: May 21, 2019Date of Patent: June 30, 2020Assignee: Infineon Technologies AGInventors: Marianne Mataln, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
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Patent number: 10658309Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.Type: GrantFiled: May 21, 2019Date of Patent: May 19, 2020Assignee: Infineon Technologies AGInventors: Marianne Mataln, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
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Publication number: 20200111754Abstract: A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.Type: ApplicationFiled: December 11, 2019Publication date: April 9, 2020Inventors: Johann Gatterbauer, Katrin Albers, Joerg Busch, Klaus Goller, Norbert Mais, Marianne Kolitsch, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
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Publication number: 20200035610Abstract: A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.Type: ApplicationFiled: July 30, 2018Publication date: January 30, 2020Inventors: Ravi Keshav Joshi, Rainer Pelzer, Axel Buerke, Sven Schmidbauer, Michael Nelhiebel
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Patent number: 10446469Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.Type: GrantFiled: July 22, 2016Date of Patent: October 15, 2019Assignee: Infineon Technologies AGInventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
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Publication number: 20190304884Abstract: A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.Type: ApplicationFiled: March 28, 2019Publication date: October 3, 2019Inventors: Silvia Larisegger, Michael Nelhiebel, Sabine Reither
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Publication number: 20190273050Abstract: A semiconductor device includes a substrate, a structured interlayer on the substrate and having a defined edge, and a structured metallization on the structured interlayer and also having a defined edge. The defined edge of the structured interlayer faces the same direction as the defined edge of the structured metallization. The defined edge of the structured interlayer extends beyond the defined edge of the structured metallization by at least 0.5 microns so that the defined edge of the structured metallization terminates before reaching the defined edge of the structured interlayer. The structured interlayer has a compressive residual stress at room temperature and the structured metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer.Type: ApplicationFiled: May 21, 2019Publication date: September 5, 2019Inventors: Marianne Mataln, Michael Nelhiebel, Rainer Pelzer, Bernhard Weidgans
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Publication number: 20190267283Abstract: According to various embodiments, a device may include: a semiconductor region; a metallization layer disposed over the semiconductor region; and a self-organizing barrier layer disposed between the metallization layer and the semiconductor region, wherein the self-organizing barrier layer comprises a first metal configured to be self-segregating from the metallization layer.Type: ApplicationFiled: May 7, 2019Publication date: August 29, 2019Inventors: Werner Robl, Michael Fugger, Carsten Schaeffer, Michael Nelhiebel, Klemens Pruegl
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Patent number: 10396067Abstract: A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor body includes a load current component having a load current transistor area and a sensor component having a sensor transistor area. The load current transistor area and the sensor transistor area share a same transistor unit construction. The load current transistor area includes first and second transistor area parts, and the sensor transistor area includes a third transistor area part. The first and the third transistor area parts differ from the second transistor area part between the first and the third transistor area parts by a load current transistor area element being absent in the second transistor area part. The second transistor area part is electrically disconnected from a parallel connection of the first and second transistor area parts by the load current transistor area element being absent in the second transistor area part.Type: GrantFiled: January 28, 2019Date of Patent: August 27, 2019Assignee: Infineon Technologies AGInventors: Stefan Decker, Robert Illing, Michael Nelhiebel