Abstract: This invention provides an outrigger assembly for fishing that can be quickly deployed from a portable bag about 1 meter long into a fully rigged outrigger in a selected length of 4 meters, 5 meters or 6 meters. Variable length is obtained by adding sections of telescoping pole. Quick deployment is obtained by using detachable line guides that are radially (or side) threadable in conjunction with a separate preassembled outrigger line loop for each deployed length. Different length outrigger line loop assemblies are color coded for quick identification. Stowed length and volume of the collapsed telescoping pole is minimized by the use of outrigger line guides that are removable from the outrigger pole. Threading and unthreading of an outrigger line loop without opening the loop is enabled by the radially threadable line guides. The invention also provides an outrigger holder having two sockets, one for the outrigger and one for a fishing pole.

Abstract: In some aspects, a system comprises a first wearable sensor configured to be attached to a first user, the first wearable sensor adapted to periodically transmit a message, the message containing a sensor identifier that uniquely identifies the first wearable sensor, wherein the first wearable sensor is configured to listen for one or more messages transmitted by one or more wearable sensors attached to other users, and wherein the first wearable sensor is adapted to determine a signal strength of a received message, and determine is the signal strength is greater than a threshold, issue an alert, and a gateway adapted to communicate with the first wearable sensor.

Abstract: This invention provides an outrigger assembly for fishing that can be quickly deployed from a portable bag about 1 meter long into a fully rigged outrigger in a selected length of 4 meters, 5 meters or 6 meters. Variable length is obtained by adding sections of telescoping pole. Quick deployment is obtained by using detachable line guides that are radially (or side) threadable in conjunction with a separate preassembled outrigger line loop for each deployed length. Different length outrigger line loop assemblies are color coded for quick identification. Stowed length and volume of the collapsed telescoping pole is minimized by the use of outrigger line guides that are removable from the outrigger pole. Threading and unthreading of an outrigger line loop without opening the loop is enabled by the radially threadable line guides. The invention also provides an outrigger holder having two sockets, one for the outrigger and one for a fishing pole.

Abstract: Methods for preparing an inhibitor of dipeptidyl peptidase IV, as well as formulations of such inhibitors of dipeptidyl peptidase IV that have a high degree of stability including under warm, humid storage conditions.

Abstract: A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.

Abstract: A folding windscreen having two panels can be made entirely from a single sheet of corrugated plastic. The windscreen is used to prevent wind-blown snow from clogging an ice-fishing hole and to enhance the visibility of ice fishing traps against a background shoreline or expanse of open ice. The single sheet of corrugated plastic material is made into two panels by folding it in half. The fold produces a flexible hinge connecting the two panels. The top and bottom edges of the windscreen panels are reinforced by folding parts of the corrugated sheet to make double thickness, and bonding the two thicknesses together with heat welding or adhesives. Hand-holes are provided for convenient carrying and deploying. Fluorescent or retro-reflective tape can be applied to the folding windscreen to enhance its visibility.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: An apparatus for testing a memory of an integrated circuit for a defect. The apparatus includes a test unit for testing a redundant memory element only when the redundant memory element has been enabled to replace a failed memory element.

Abstract: Methods and apparatuses for enabling a redundant memory element (20) during testing of a memory array (14). The memory array (14) includes general memory elements (18) and redundant memory elements (20). The general memory elements (18) are tested and any defective general memory elements (18) are replaced with redundant memory elements (20). The redundant memory elements (20) are tested only when they are enabled.

Abstract: A memory array for an integrated circuit includes a plurality of memory elements includes at least one redundant memory element for exchanging with a failed memory element in the plurality of memory elements. A failing address repair register is provided, having a register for controlling enablement of a corresponding redundant memory element and compare logic for determining whether an address of a failing memory element is stored in the register.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.

Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded.

Abstract: Keyword-based verification of proper connectivity of a circuit design including a plurality of cells is disclosed. In one embodiment, a method includes assigning a keyword to each relevant pin of the circuit design, the keyword indicates a verification rule for a domain starting at the relevant pin; tracing the domain starting at the relevant pin, including recording a circuit instance identifier of each cell encountered to generate a traced circuit instance set; and verifying proper connectivity using the verification rule and the traced circuit instance set. The keyword may also indicate a name that drives the creation of a domain, or a trace rule that instructs the tracing. If the traced circuit instance sets do not match the pre-defined relationships, the verification fails and the user is notified that the logic must be modified. The keyword-based verification can occur between domains of the same circuit or a traced circuit instance set can be compared to an expected set.

Abstract: A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.

Abstract: Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.