Abstract: An integrated circuit incorporating test access provisions and a system addressable command control register; and provisions for selectably enabling and accessing one or the other for purposes of evaluating integrated circuit functionality.

Abstract: A hybrid cache/SIRO buffer system includes a latch array for storing data words corresponding to system addresses; read command generator circuitry for launching data read commands to a memory system; a write pointer; write circuitry for storing data arriving from the memory system into the latch array at the location indicated by the write pointer; lowest and highest pointers for indicating the locations in the latch array corresponding to a lowest and a highest system address for which a read command has been launched; read circuitry for retrieving data from the latch array randomly; and control circuitry. Responsive to a first read request by a host system, the system begins retrieving data from memory beginning with an address equal to or close to the address associated with the first read request; then it speculatively reads ahead. As read requests from the host system continue to be processed by the system, more speculative reads are executed until the buffer is nearly full of data.

Abstract: A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

Abstract: A method and apparatus for transferring a block of pixel data from a source multi-line frame buffer area to a destination multi-line frame buffer area in a raster-type computer graphics display system. The method steps are performed by a state machine embedded in a macro function unit within a computer graphics subsystem: It is first determined whether the first raster line corresponding to the destination multi-line frame buffer area is at least a minimum number of raster lines ahead of the current raster line. If so, the state machine follows a fast path, during which the pixel data are transferred one line at a time from the source multi-line frame buffer area to the destination multi-line frame buffer area until the last line of pixel data in the block has been transferred. Then, the transfer operation stops. If not, then the state machine follows a slow path.

Abstract: A system is provided for achieving high speed data transfers from a host memory to an ancillary processor, where the ancillary processor is preferably a geometry accelerator of a graphics machine. In accordance with a preferred embodiment, the system includes at least one memory segment having at least one enable bit and a starting address. The system further includes a data transfer queue defined in a portion of the host memory beginning at the starting location, where the data transfer queue has at least one header portion and at least one data portion, the header portion including at least one data ready bit that is indicative of whether the associated block of data is ready to be transferred to the ancillary processor.

Abstract: A scan line generator for area fill of a polygon defined by a left edge and a right edge includes a Bresenham-like mechanism in a left edge machine for selecting pixels to represent a left edge by determining, for each scan line, which pixel is either on the edge or immediately to the right thereof. A right edge machine contains an identical mechanism, which also does "to-the-right-of". Both edge machines operate in the first through fourth octants, and a coordination mechanism steps the two edge machines a scan line at a time, independent of the major and minor axis of each edge. When the pixel addresses for each edge's intersection with the next scan line are found their difference along the X axis is obtained to produce the length of a fill vector on that scan line. The intersection produced for the left edge is taken as the starting point of the fill vector. Left and right edges must initially start on the same scan line, but need not be of the same length in the Y axis.

Abstract: An interface unit which can reduce the hardware cost by interfacing a microprocessor with an inexpensive memory device with a smaller word size without compromising the overall performance. The current invention improves the overall performance of the interface system by reducing the overhead address relatching without adding expensive and sophisticated pieces of hardware. This is accomplished by comparing a row address portion of the current address with that of the previous address. When a current address contains the same row address as the previously accessed memory-page, the current invention saves clock cycles by avoiding relatching of the row address portion of the address in the memory device. Such saving is significant when contiguous addresses are sequentially accessed.