Patents by Inventor Michael R. Trombley
Michael R. Trombley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9436388Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: April 7, 2016Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20160216897Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 9343123Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: September 10, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Patent number: 9128868Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.Type: GrantFiled: January 31, 2008Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd
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Publication number: 20140379979Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8902683Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: August 27, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20130346686Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8547760Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: June 29, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Patent number: 8516338Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.Type: GrantFiled: June 28, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Peter Buchmann, Kevin C. Gower, Robert J. Reese, Martin L. Schmatz, Michael R. Trombley
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Publication number: 20130003475Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven K. Jenkins, Robert B. Likovich, JR., Michael R. Trombley
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Publication number: 20120272119Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.Type: ApplicationFiled: June 28, 2012Publication date: October 25, 2012Inventors: Peter Buchmann, Kevin C. Gower, Robert J. Reese, Martin L. Schmatz, Michael R. Trombley
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Patent number: 8245105Abstract: A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.Type: GrantFiled: July 1, 2008Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Kevin C. Gower, Warren E. Maule, Michael R. Trombley
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Patent number: 8234540Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.Type: GrantFiled: July 1, 2008Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Peter Buchmann, Kevin C. Gower, Robert J. Reese, Martin L. Schmatz, Michael R. Trombley
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Patent number: 8181094Abstract: A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.Type: GrantFiled: January 31, 2008Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
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System to improve miscorrection rates in error control code through buffering and associated methods
Patent number: 8176391Abstract: A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.Type: GrantFiled: January 31, 2008Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Irving G. Baysah, Timothy J. Dell, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright -
Patent number: 8140825Abstract: Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.Type: GrantFiled: August 5, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Ganesh Balakrishnan, Anil Krishna, Michael R. Trombley
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Patent number: 8139430Abstract: A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.Type: GrantFiled: July 1, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Peter L. Buchmann, Frank D. Ferraiolo, Kevin C. Gower, Robert J. Reese, Eric E. Retter, Martin L. Schmatz, Michael B. Spear, Peter M. Thomsen, Michael R. Trombley
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Patent number: 8140803Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.Type: GrantFiled: May 4, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Patent number: 8099570Abstract: Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.Type: GrantFiled: February 22, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: James A. O'Connor, Kanwal Bahri, Daniel J. Henderson, Luis A. Lastras-Montano, Warren E. Maule, Michael Mueller, Naresh Nayar, Richard Nicholas, Eric E. Retter, William J. Starke, Michael R. Trombley, Kenneth L. Wright
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Patent number: 8032713Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.Type: GrantFiled: May 5, 2008Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley