Patents by Inventor Michael Raymond Trombley
Michael Raymond Trombley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11838153Abstract: A digital signal processor includes analog to digital converters to convert an analog voltage to digital voltage in unit intervals of an analog signal. A decision feedback equalizer (DFE) determines a first level of a digital sum of a digital voltage in a first UI and digital voltages of adjacent UIs (taps). The DFE identifies predetermined sequences of levels of consecutive UIs that include the first level and selects one of the predetermined sequences to decode digital data encoded in the analog signal in the UI. The DSP may be programmable to include taps from UIs that may affect the first UI. The predetermined sequences may include levels of the digital sums of consecutive UIs of the analog signal. The predetermined sequences may be identified in a look-up table based on the first level.Type: GrantFiled: June 29, 2022Date of Patent: December 5, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Md Masum Hossain, Charles Boecker, Michael Raymond Trombley, Simon S. Li, Shaishav A. Desai
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Patent number: 10804919Abstract: A time-interleaved SAR-ADC employs calibrated SAR-ADC circuits to convert sampled voltage levels into serial digital data. Variable delay clock circuits synchronize clock signals received at the respective SAR-ADCs to sampling points of analog serial data. IC and environmental fluctuations cause delay in the variable delay clock circuits to skew the clock signals. A calibrated SAR-ADC detects changes to the delays in the variable delay clock circuits. By delaying a first clock signal in the variable delay clock circuit, and comparing a phase of the delayed clock signal to a phase-shifted clock signal having a known phase shift relative to the first clock signal, a change in the delay of the variable delay clock circuit can be detected as a phase difference. Based on an indication of a phase difference, a delay control signal is generated to control the delay in the variable delay clock.Type: GrantFiled: September 24, 2019Date of Patent: October 13, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Hayden Cranford, Michael Raymond Trombley
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Patent number: 10236917Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.Type: GrantFiled: September 15, 2016Date of Patent: March 19, 2019Assignee: QUALCOMM IncorporatedInventors: Natarajan Vaidhyanathan, Luther James Blackwood, Mattheus Cornelis Antonius Adrianus Heddes, Michael Raymond Trombley, Colin Beaton Verrilli
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Publication number: 20180074893Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.Type: ApplicationFiled: September 15, 2016Publication date: March 15, 2018Inventors: Natarajan Vaidhyanathan, Luther James Blackwood, Mattheus Cornelis Antonius Adrianus Heddes, Michael Raymond Trombley, Colin Beaton Verrilli
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Patent number: 9710324Abstract: A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.Type: GrantFiled: September 17, 2015Date of Patent: July 18, 2017Assignee: QUALCOMM IncorporatedInventor: Michael Raymond Trombley
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Publication number: 20160224241Abstract: Providing memory bandwidth compression using back-to-back read operations by compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from error correcting code (ECC) bits of a first memory block in a memory line associated with the physical address. Based on the CI, the CMC determines whether the first memory block comprises compressed data. If not, the CMC performs a back-to-back read of one or more additional memory blocks of the memory line in parallel with returning the first memory block. Some aspects may further improve memory access latency by writing compressed data to each of a plurality of memory blocks of the memory line, rather than only to the first memory block.Type: ApplicationFiled: September 3, 2015Publication date: August 4, 2016Inventors: Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Brian Joel Schuh, Michael Raymond Trombley, Natarajan Vaidhyanathan
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Publication number: 20160224414Abstract: A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.Type: ApplicationFiled: September 17, 2015Publication date: August 4, 2016Inventor: Michael Raymond Trombley
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Patent number: 9053031Abstract: A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold.Type: GrantFiled: December 10, 2007Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: James Johnson Allen, Jr., Steven Kenneth Jenkins, James A. Mossman, Michael Raymond Trombley
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Patent number: 8122216Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.Type: GrantFiled: September 6, 2006Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: David Michael Daly, Peter Anthony Franaszek, Michael Ignatowski, Luis Alfonso Lastras-Montano, Michael Raymond Trombley
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Patent number: 7949830Abstract: A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.Type: GrantFiled: December 10, 2007Date of Patent: May 24, 2011Assignee: International Business Machines CorporationInventors: James Johnson Allen, Jr., Steven Kenneth Jenkins, James A. Mossman, Michael Raymond Trombley
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Publication number: 20090150622Abstract: A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: International Business Machines CorporationInventors: James Johnson Allen, JR., Steven Kenneth Jenkins, James A. Mossman, Michael Raymond Trombley
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Publication number: 20090150401Abstract: A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: International Business Machines CorporationInventors: James Johnson Allen, JR., Steven Kenneth Jenkins, James A. Mossman, Michael Raymond Trombley
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Publication number: 20080098176Abstract: A method and apparatus implement memory accesses to a memory using an open page mode with data prefetching. A central processor unit issues memory commands. A memory controller receiving the memory commands, identifies a data prefetching command. The memory controller checks whether a next sequential line for the identified prefetch command is within the page currently being accessed, and responsive to identifying the next sequential line being within the current page, the current command is processed and the current page left open.Type: ApplicationFiled: October 18, 2006Publication date: April 24, 2008Inventors: M. V. V. Anil Krishna, Michael Raymond Trombley, Steven Paul VanderWeil
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Publication number: 20080059728Abstract: Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.Type: ApplicationFiled: September 6, 2006Publication date: March 6, 2008Inventors: David Michael Daly, Peter Anthony Franaszek, Michael Ignatowski, Luis Alfonso Lastras-Montano, Michael Raymond Trombley
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Patent number: 6766381Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.Type: GrantFiled: August 27, 1999Date of Patent: July 20, 2004Assignee: International Business Machines CorporationInventors: Kenneth James Barker, Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Michael Steven Siegel, Michael Raymond Trombley, Fabrice Jean Verplanken
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Patent number: 6601229Abstract: A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.Type: GrantFiled: March 9, 2000Date of Patent: July 29, 2003Assignee: International Business Machines CorporationInventors: Theron Paul Niederer, Raj Kumar Singh, Michael Raymond Trombley
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Patent number: 6584518Abstract: A method and system for queueing data within a data storage device including a set of storage blocks each having an address, a pointer field, and a data field. This set of storage blocks comprises a linked list of associated storage blocks and also a free pool of available storage blocks. The storage device further includes a tail register for tracking an empty tail block from which a data object is enqueued into the linked list. A request to enqueue a data object into the linked list is received within the data storage system. In response to the data enqueue request, an available storage block from the free pool is selected and associated with the tail register. A single write operation is then required to write the data object into the data field of a current tail block and to write the address of the selected storage block into the pointer field of the current tail block, such that the selected storage block becomes a new tail block to which the tail register points.Type: GrantFiled: January 7, 2000Date of Patent: June 24, 2003Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Michael Steven Siegel, Michael Raymond Trombley, Fabrice Jean Verplanken
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Patent number: 6557053Abstract: A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.Type: GrantFiled: January 4, 2000Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Michael Steven Siegel, Michael Raymond Trombley, Fabrice Jean Verplanken
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Patent number: 6473838Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.Type: GrantFiled: January 4, 2000Date of Patent: October 29, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Steven Kenneth Jenkins, Michael Steven Siegel, Michael Raymond Trombley, Fabrice Jean Verplanken