Patents by Inventor Michael Rendon

Michael Rendon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7262105
    Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: August 28, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dharmesh Jawarani, Nigel G. Cave, Michael Rendon
  • Publication number: 20050112829
    Abstract: In a semiconductor device, a relatively deep germanium implant and activation thereof precedes deposition of the nickel for nickel silicide formation. The activation of the germanium causes the lattice constant in the region of the implant to be increased over the lattice constant of the background substrate, which is preferably silicon. The effect is that the lattice so altered avoids formation of nickel disilicide. The result is that the nickel silicide spiking is avoided.
    Type: Application
    Filed: November 21, 2003
    Publication date: May 26, 2005
    Inventors: Dharmesh Jawarani, Nigel Cave, Michael Rendon
  • Publication number: 20050056899
    Abstract: An insulating layer (24, 66, 82) is formed over a stack (14) of materials and a semiconductor substrate (12) and an implant is performed through the insulating layer into the semiconductor substrate. In one embodiment, spacers (26) are formed over the insulating layer (24), the insulating layer (24) is etched, and heavily doped regions (36) are formed adjacent the spacers. The spacers (26) are then removed and extension regions (50) and optional halo regions (46) are formed by implanting through the insulating layer (24). In one embodiment, the insulating layer (24) is in contact with the semiconductor substrate (12). In one embodiment, the stack (14) is a gate stack including a gate dielectric (18), a gate electrode (16), and an optional capping layer (22). The insulating layer (24, 66, 82) may include nitrogen, such as silicon nitride and aluminum nitride. In another embodiment, the insulating layer (24, 66, 82) may be hafnium oxide.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 17, 2005
    Inventors: Michael Rendon, John Grant, Ross Noble