Patents by Inventor Michael Rosenfield

Michael Rosenfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8949837
    Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Orran Yaakov Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi, Balaram Sinharoy, Robert Brett Tremaine
  • Publication number: 20120198459
    Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
    Type: Application
    Filed: March 29, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick Joseph Bohrer, Orran Yaakov Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi, Balaram Sinharoy, Robert Brett Tremaine
  • Patent number: 8230422
    Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: July 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Patrick Joseph Bohrer, Orran Yaakov Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi, Balaram Sinharoy, Robert Brett Tremaine
  • Publication number: 20060155963
    Abstract: A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
    Type: Application
    Filed: January 13, 2005
    Publication date: July 13, 2006
    Inventors: Patrick Bohrer, Orran Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi, Balaram Sinharoy, Robert Tremaine
  • Patent number: 4914422
    Abstract: A personal alert safety system (PASS) of the type carried by firefighters, rescuers, and the like. The unit attaches to the firefighters shoulder harness and is characterized by its ability to indicate audibly temperature changes in 100.degree. F. increments within the hazardous environment, as well as lack of motion by the firefighter. The activating circuit includes a horn alarm signalling both temperature changes and lack of motion, such that both the firefighter, as well as his colleagues, may be audibly apprised.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: April 3, 1990
    Inventors: Daniel Rosenfield, Michael Rosenfield