Abstract: A timer circuit, comprises a delay indication circuit, a frequency indication circuit, and a plurality of counters. The delay indication circuit is for providing a delay time indication. The frequency indication circuit is for providing a frequency indication of a frequency of a clock signal. Each counter of the plurality of counters includes a load input to receive an initial value, and an indication output to provide a count complete indication of the counter. During operation a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired. At least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set.

Abstract: A timer circuit, comprises a delay indication circuit, a frequency indication circuit, and a plurality of counters. The delay indication circuit is for providing a delay time indication. The frequency indication circuit is for providing a frequency indication of a frequency of a clock signal. Each counter of the plurality of counters includes a load input to receive an initial value, and an indication output to provide a count complete indication of the counter. During operation a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired. At least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set.

Abstract: A method of a processor communicating data across a bus bridge to a processing apparatus on a bus including the steps of storing the data into a processor memory, notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, reading the data from the processor memory upon request of the bus bridge, and forwarding the data from the bus bridge to the processing apparatus across the bus. In addition, an apparatus for a processor to communicate data across a bus bridge to a processing means on a bus including an apparatus for storing the data into a processor memory, an apparatus for notifying the bus bridge, coupled to the processor and a bus, that the data is in the processor memory, an apparatus for reading the data from the processor memory upon request of the bus bridge, and an apparatus for forwarding the data from the bus bridge to the processing apparatus across the bus.