Abstract: Embodiments of the invention relate to hosting a competition on a computing device, wherein the competition allows participants to select a first set of predicted winners for a predetermined series of matches in a tournament and a second set of predictions for winners if one or more of the first set of predicted winners are eliminated earlier than predicted. The competition may be implemented in any suitable computing system environment, including, but not limited to, a web-based competition hosted on a remote server, a private or company-based competition hosted on a private or company computer.

Abstract: An array of dynamic memory cells and method for programming that array with initial information, as well as a disk drive system incorporating such an array, are disclosed. The array includes dynamic memory cells formed on an integrated circuit substrate. The array is modified by a programming step to contain nonvolatile initial information which may be retrieved immediately following a reset sequence. The array includes storage cells arranged as a matrix of bit line columns and row selects, each cell including a pass transistor having a predetermined threshold voltage characteristic Vth and being associated with a storage capacitor. Predetermined ones of the pass transistors are modified by a programming step, either during or following fabrication, so as to have a different predetermined threshold voltage characteristic Vthm, so that the array is comprised of unmodified cells and modified cells in a manner defining nonvolatile initial information in the array.

Abstract: A duty cycle equalization circuit equalizes the duty cycle of an incoming two-level logic driving signal and includes a CMOS current source having source electrodes connected to receive the two-level logic driving signal and having drain electrodes connected to a sawtooth signal forming path, a sawtooth wave forming circuit element, such as a capacitor, connected to the sawtooth signal forming path for forming a sawtooth waveform, a reference voltage circuit, such as a low pass filter, for generating a reference voltage level as a function of the two-level logic driving signal, and a differential comparator circuit element connected to receive the sawtooth waveform at a data input thereof, and to receive the reference voltage at a reference signal input thereof, and to put out a logical signal timed to correspond with crossings of the sawtooth signal through the reference voltage level.