Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: A processing cell for use in computing systems is disclosed. Generally, a processing cell generates branch commands to be received and processed by at least one other processing cell. A processing cell may be instruction-based that includes a program counter, an instruction memory, and appropriate elements such as a branch lookup, a branch unit, an ALU, etc., for computations. Alternatively, the processing cell is state-machine based, which is comparable to an instruction-based cell, but includes a state machine that replaces the program counter and the instruction memory. Embodiments of the invention are able to support at least the VLIW mode, the MIMD mode, and a mixture of both modes of execution.

Abstract: A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality of transport cells that can be configured to implement various transport networks, one for a particular memory application. To implement different memory applications in the same configurable memory system, a system designer takes several steps. The system designer identifies memory applications to be implemented in the configurable memory system. For each memory application, the designer allocates a set of memory modules and a transport network carrying data for the memory modules. Each transport network corresponding to a memory application thus establishes the data paths to and from the memory modules for that memory application.

Abstract: A technique for synthesizing digital circuit designs by incorporating timing convergence and routability considerations. In one aspect, the invention provides a system and programmatic method for generating a circuit design from a functional specification according to at least one design objective. An intermediate representation of the functional specification is formed. The intermediate representation is analyzed for identifying a physical instantiation that will possibly result in unacceptable interconnect delay or congestion. Functional units are allocated from among a plurality of candidate functional units for performing operations of the intermediate representation. Operations are scheduled to occur at specified times on said selected functional units. An architectural representation of the circuit design is formed according to results of scheduling.

Abstract: One embodiment of the invention is a method for forming a solver for a loop nest of code, the method comprising forming a time and space mapping of a portion of the loop nest, performing at least one optimization that is dependent on the time and space mapping to the portion of the loop nest, and forming a solver from the optimized portion of the loop nest.

Abstract: The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the plurality of processing elements generates a branch command. The invention uses a programmable network that transports the branch command from the processing element to one of a first destination processing element by a first programmed transport route and a second destination processing element by a second programmed transport route. The branch command is received and processed by one of the first destination processing element and the second destination processing element, and is not processed by the other of the first processing element and the second processing element.

Abstract: The invention is a system and method for executing a program that comprises a plurality of basic blocks on a computer system that comprises a plurality of processing elements. The invention generates a branch instruction by one processing element of the plurality of processing elements, sends the branch instruction to the plurality of processing elements. The invention then independently branches to a target of the branch instruction by each of the processing elements of the plurality of processing elements when each processing element receives the sent branch instruction. At least one processing element of the plurality of processing elements receives the branch instruction at a time later than another processing element of the plurality of processing elements.

Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: A computer-implemented method automates the design of efficient binary instruction encodings of VLIW instruction formats. The method automatically finds compact instruction formats that can express and exploit the full parallelism specified in the underlying processor microarchitecture, subject to constraints on alignment and decode hardware complexity. The method can be guided by statistics about the composition and frequency of program instructions, so that the instruction format design is customized to a particular set of applications or an application domain.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.

Abstract: A VLIW processor design system automates the design of programmable and non-programmable VLIW processors. The system takes as input an opcode repertoire, the I/O format of the opcodes, a register file specification, and instruction-level parallelism constraints. With this input specification, the system constructs a datapath, including functional units, register files and their interconnect components from a macrocell database. The system uses the input and the datapath to generate an instruction format design. The instruction format may then be used to construct the processor control path. The abstract input and datapath may be used to extract a machine description suitable to re-target a compiler to the processor. To optimize the processor for a particular application program, the system selects custom instruction templates based on operation issue statistics for the application program generated by the re-targeted compiler.

Abstract: A technique for flexible scheduling of a code sequence wherein a set of instructions for determining a a fully-resolved predicate for each of a set of non-speculative instructions contained in the code sequence is generated. An optimized code sequence is then generated that includes the instructions for determining the fully resolved predicates and that further includes the non-speculative instructions each guarded by one of the fully resolved predicates such that any one of the non-speculative instructions may be executed before any other of the non-speculative instructions.

Abstract: A compiler of a predicated code includes a data flow analysis system that manipulates and queries predicate expressions of the predicated code to (1) analyze data flow properties of the predicated code and (2) annotate the predicated code with the analyzed data flow properties. A predicate-sensitive analyzer for a compiler that compiles a predicated code is also described. The predicate-sensitive analyzer includes a scanner that determines local predicate relations of the predicated code. The analyzer also includes a builder that determines global predicate relations of the predicated code. A predicate query system is provided to store the local and global predicate relations of the predicated code and to answer queries about the local and global predicate relations. A method of compiling the predicated code is also described.

Abstract: A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming execution of multiple branch instructions by a target processor.

Abstract: A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Abstract: A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.