Patents by Inventor Michael Steven Schlansker
Michael Steven Schlansker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9161105Abstract: Systems, methods, and apparatus to route optical signals are disclosed. An example apparatus to route optical signals includes a plurality of hollow metal waveguide optical switch arrays. Each of the arrays comprises a plurality of optical input ports and a plurality of optical output ports. The input ports and the output ports for a first one of the arrays are arranged in a first plane, the input ports and the output ports for a second one of the arrays are arranged in a second plane, and the plurality of arrays are stacked such that the first and second planes are adjacent. The first one of the arrays is to convey optical signals from a first communication device to a second communication device and the second one of the arrays is to convey optical signals from the second communication device to the first communication device.Type: GrantFiled: April 11, 2012Date of Patent: October 13, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Terrel Morris, Michael Renne Ty Tan, Shih-Yuan Wang, Michael Steven Schlansker
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Patent number: 9137179Abstract: Systems and methods for providing network interface controllers (NICs) with memory-mapped buffers are described. A processing system includes a plurality of processing cells, each including at least one processor and at least one system memory. A NIC is associated with each of the processing cells for transmitting and receiving data between the processing cells. Each of the cells further includes a memory interconnect to which the NIC is directly connected and the NIC includes at least one memory-mapped buffer.Type: GrantFiled: July 26, 2006Date of Patent: September 15, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael Steven Schlansker, Erwin Oertli
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Publication number: 20140369682Abstract: Systems, methods, and apparatus to route optical signals are disclosed. An example apparatus to route optical signals includes a plurality of hollow metal waveguide optical switch arrays. Each of the arrays comprises a plurality of optical input ports and a plurality of optical output ports. The input ports and the output ports for a first one of the arrays are arranged in a first plane, the input ports and the output ports for a second one of the arrays are arranged in a second plane, and the plurality of arrays are stacked such that the first and second planes are adjacent. The first one of the arrays is to convey optical signals from a first communication device to a second communication device and the second one of the arrays is to convey optical signals from the second communication device to the first communication device.Type: ApplicationFiled: April 11, 2012Publication date: December 18, 2014Applicant: Hewlett-Packard Development Company, L.P.Inventors: Terrel Morris, Michael Renne Ty Tan, Shih-Yuan Wang, Michael Steven Schlansker
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Publication number: 20140314417Abstract: An optical connection infrastructure has optical conduits between first devices and at least one second device. Dynamic reconfiguration of the optical connection infrastructure can be performed from a first connection topology to a second, different connection topology based on programming of the first devices.Type: ApplicationFiled: April 12, 2012Publication date: October 23, 2014Inventors: Kevin B. Leigh, David Jay Koenen, Guodong Zhang, Michael Steven Schlansker, Jean Tourrilhes, Gary William Thome, Ian Moray McLaren
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Publication number: 20130272651Abstract: Systems, methods, and apparatus to route optical signals are disclosed. An example apparatus to route optical signals includes a plurality of hollow metal waveguide optical switch arrays, the arrays being stacked, each of the arrays including: a first number of optical input ports; and a second number of optical output ports different than the first number of input ports.Type: ApplicationFiled: April 11, 2012Publication date: October 17, 2013Inventors: Terrel Morris, Michael Steven Schlansker, Michael Renne Ty Tan, Shih-Yuan Wang
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Patent number: 8364874Abstract: Methods and systems for prioritizing virtual network interface controllers (VNICs) are described. Each VNIC is assigned a priority level and a maximum current priority level associated with VNICs which are requesting service is determined. Fairness is enforced by using a round robin approach to selection among those currently requesting VNICs which have the same, maximum current priority level.Type: GrantFiled: January 17, 2006Date of Patent: January 29, 2013Assignee: Hewlett-Packard Development Company, L. P.Inventors: Michael Steven Schlansker, Jean-Francois Collard, Rajendra Kumar
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Patent number: 7962656Abstract: Methods and systems for communicating between network interface controllers (NICs) in networked systems are described. Enhanced command functionality for NICs include the ability to perform sequences of operations and/or conditional operations. Messages can be used to communicate embedded commands which are interpreted by NICs to enhance their functionality.Type: GrantFiled: January 3, 2006Date of Patent: June 14, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Boon Seong Ang, Michael Steven Schlansker, Robert Samuel Schreiber, Jean-Francois Collard, Norman Paul Jouppi
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Patent number: 7912998Abstract: Methods and systems for performing direct memory access (DMA) transfers are described. An invalidate queue (or other storage device) contains an entry associated with a DMA transfer in progress. If the invalidate queue detects an invalidation of a memory page associated with that entry, then it is marked invalid. If the entry is marked invalid during the DMA transfer, then that DMA transfer is aborted. This enables, among other things, DMA transfers to unpinned virtual memory.Type: GrantFiled: January 6, 2006Date of Patent: March 22, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael Steven Schlansker, Erwin Oertli, Jean-Francois Collard
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Patent number: 7650471Abstract: A technique includes identifying an address of a head end of a queue and monitoring a coherent interconnect to identify a data transfer that is communicated by a producer, which targets the address. The technique includes storing the data of the data transfer in the queue and selectively storing at least a portion of the data in a head-of-queue cache memory based at least in part on whether the monitoring identifies the address. At least a portion of the data is selectively retrieved from the head-of-queue cache memory instead of from the queue for transmission to a consumer.Type: GrantFiled: January 6, 2006Date of Patent: January 19, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael Steven Schlansker, Erwin Oertli, Jean-Francois Collard
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Publication number: 20080028103Abstract: Systems and methods for providing network interface controllers (NICs) with memory-mapped buffers are described. A processing system includes a plurality of processing cells, each including at least one processor and at least one system memory. A NIC is associated with each of the processing cells for transmitting and receiving data between the processing cells. Each of the cells further includes a memory interconnect to which the NIC is directly connected and the NIC includes at least one memory-mapped buffer.Type: ApplicationFiled: July 26, 2006Publication date: January 31, 2008Inventors: Michael Steven Schlansker, Erwin Oertli
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Patent number: 7024538Abstract: A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. Each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.Type: GrantFiled: December 21, 2001Date of Patent: April 4, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Michael Steven Schlansker
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Patent number: 6766445Abstract: A computational unit for use in loop computations. The computational unit includes a function unit, a plurality of phase lines, and a storage register. The computational unit is programmed to initiate one iteration of the loop every II cycles. Each function unit has a result output for outputting one computational result each cycle. There is one phase line corresponding to each of the II cycles. The storage register includes a linear connected array of shift cells having a first shift cell. Each shift cell has an input port, an output port, a shift control port, and an OR gate. Each shift cell receives the value to be stored in the shift cell on the input port, the stored value being stored in response to a control signal on the shift control port. The OR gate has an output connected to the shift enable port and one input for each cycle on which that shift cell is to receive the control signal, that input being connected to the phase line corresponding to that cycle.Type: GrantFiled: March 23, 2001Date of Patent: July 20, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael Steven Schlansker, Vinod Kumar Kathail, Shail Aditya Gupta
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Publication number: 20030120897Abstract: A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventor: Michael Steven Schlansker
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Publication number: 20020138718Abstract: A computational unit for use in loop computations. The computational unit includes a function unit, a plurality of phase lines, and a storage register. The computational unit is programmed to initiate one iteration of the loop every II cycles. Each function unit has a result output for outputting one computational result each cycle. There is one phase line corresponding to each of the II cycles. The storage register includes a linear connected array of shift cells having a first shift cell. Each shift cell has an input port, an output port, a shift control port, and an OR gate. Each shift cell receives the value to be stored in the shift cell on the input port, the stored value being stored in response to a control signal on the shift control port. The OR gate has an output connected to the shift enable port and one input for each cycle on which that shift cell is to receive the control signal, that input being connected to the phase line corresponding to that cycle.Type: ApplicationFiled: March 23, 2001Publication date: September 26, 2002Inventors: Michael Steven Schlansker, Vinod Kumar Kathail, Shail Aditya Gupta