Abstract: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.

Abstract: In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.

Abstract: A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified, where a fan node is defined as a point of interconnection between two or more of the plurality of transistors from which multiple nonredundant current paths to power, ground, or an input of the circuit exist. A fan node equation set is constructed that expresses a logical state of each fan node of the circuit in response to various transistor gate signal states. In addition, an output node equation is constructed that expresses a logical state of an output node of the circuit in terms of selected fan node logical states and specified transistor gate signal states.

Abstract: A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation.

Abstract: A system and method for selecting a processor to service interrupts in a multiprocessor system with processor individualized interrupt priority states. The interrupt priority information associated with the various processors is bit serially compared to select one or more processors of lowest interrupt priority status, Processor individualized identification information is then compared to reconcile when multiple processors have an identical interrupt priority level, The outcome is stored and immediately available for managing interrupts generated by I/O devices, In a preferred arrangement, the interrupt priority status of the selected processor is confirmed immediately before processing the service requests to compensate for any changes occurring during the period of the bit serial comparison.

Abstract: The invention is a system and method for providing a breakpoint exception at any predetermined instruction address in a processor system of the type including an integrated circuit microprocessor and an instruction cache and memory management unit (CMMU) where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced in the microprocessor in response to the FAULT code reply signal.