Abstract: A power management unit is provided that monitors various portions of a computer system and causes a reduction in the frequencies of the CPU clock signal and the system clock signal during a power conserving state. The power management unit includes a programmable counter for allowing the system designer to vary the length of a wake-up period that occurs in response to an assertion of a timer tick interrupt. An in-service register of an interrupt controller is coupled to the power management unit which thereby allows the power management unit to receive real-time information regarding whether a timer tick interrupt is currently being serviced by the microprocessor. When a timer tick status bit of the in-service register is set, the power management unit causes the CPU clock signal and the system clock signal to be driven at maximum frequencies. When the timer tick status bit clears, the programmable counter begins counting.

Abstract: A system and method for controlling a peripheral bus clock signal through a master and/or slave device is provided that accommodates a power conservation (or "clock run") scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. The clock run feature is enabled or disabled by the system during or immediately following system initialization, based upon the ability of the peripheral bus components to support the clock run feature. The system includes status and command registers to provide an indication of whether each of the peripheral bus devices can support the power conservation scheme. The status and command registers both include a bit dedicated to the clock run function. The status register bit is set based upon whether that particular device can support the clock run function.

Abstract: A memory control unit (MCU) detects whether each bank of a DRAM subsystem will support parity error checking, and based on this determination, selectively disables the system parity error checking for those banks which do not support parity. The MCU automatically enables the system parity error checking for any banks that do support parity error checking. The memory control unit advantageously eliminates the need for the user to know what types of DRAM are in the system or how to configure the system to operate with the current DRAM types. Furthermore, the memory control unit allows for selective generation of parity checking among DRAM banks depending upon which banks support parity. Accordingly, even if one or more DRAM banks do not support parity, the capabilities of those DRAM banks that support parity will not go unused, and the advantages attained by parity error checking will be realized for the DRAM banks that support parity.

Abstract: A periodic system management interrupt (SMI) source is provided that includes a programmable timer for asserting an SMI a predetermined rate. A microprocessor is coupled to a periodic SMI source through a CPU local bus. The periodic SMI source may be programmed by executing an I/O write cycle which allows a count value and an enable bit to be loaded into an internal configuration register. When the enable bit is set, the programmable timer asserts a periodic system management interrupt at a fixed rate as determined by the count value within the configuration register. The periodic system management interrupt may be asserted, for example, at intervals of 16 milliseconds, 64 milliseconds, 245 milliseconds, 1 second, 16 seconds, or 1 minute. The periodic SMI source allows for the automatic generation of a periodic system management interrupt independently of software.

Abstract: A power management unit is provided that includes several states, each of which is associated with a different power management mode. Transitions between the states of the power management unit are dependent upon the type of activities detected. Upon reset of the computer system, the power management unit enters a ready state during which a CPU clock signal and a system clock signal are driven at their maximum frequencies. If no primary activities are detected over certain time periods, the power management unit successively transitions from the ready state to a doze state, then to a stand-by state, and then to a suspend state. During the doze state, the frequency of the CPU clock signal is slowed, and during the stand-by state, the CPU clock signal is stopped. During the suspend state, both the CPU clock signal and the system clock signal are stopped, and the power to selected circuit portions may be removed.

Abstract: A power management unit including a set of time-out counters and a software configurable state register is provided for managing power consumption within a computer system. Depending upon the state of the power management unit, a power control unit and a clock control unit are configured such that power may be applied or removed from certain components of the computer system and such that the frequencies of a CPU clock signal and a system clock signal may be raised or lowered. The power management unit includes a software configurable state register which allows system software, such as APM responsive software within the system BIOS, to control the state of the power management unit. When the power management unit is in a ready state during which the CPU clock signal and the system clock signal are driven at maximum frequencies and during which power is applied to all computer components, a time-out counter is activated to begin a first count down period.

Abstract: A computer system is provided that employs a disable technique which warns the user of a low battery condition when the user attempts to power-on the computer, and which prevents power from being applied to a primary portion of the computer system. A battery monitor is included for monitoring the voltage across the battery, and for asserting a control signal when the battery voltage drops below a certain threshold value. A control unit receives the control signal and accordingly prevents power from being applied to a primary computer subsystem when the computer system is turned on. Instead, when the user attempts to turn on the computer system when the low battery-capacity condition exists, the control unit causes a pulse generator to generate a signal that drives a speaker. An audible indication of the low power condition is thereby produced.

Abstract: A set of I/O indexed configuration registers are provided within a real time clock circuit of a computer system to allow the storage of the day, month and century for an alarm activation event. The I/O indexed configuration registers that store the alarm year, the alarm month, and the alarm day information are shadowed with respect to the I/O indexed configuration registers that store the current year, month, and day information for the real time clock circuit. An additional configuration register mapped within the configuration space of the computer system is provided that stores a bit that controls whether the configuration registers for the current year, month, and day will be accessed during an I/O cycle to a predetermined address of the indexed configuration registers, or whether the configuration registers for the alarm year, alarm month, and alarm day will be accessed during an I/O cycle to the predetermined address.