Abstract: A cache memory system 22 is described in which a content addressable memory 24 and a cache RAM memory 28 are provided. Each content addressable storage row has an associated hit line 18 and an access enable line 12. An index decoder 46 is provided for controlling cache replacement and cache maintenance operations. The hit line 18 is used for passing both hit signals to the cache RAM 28 and select signals generated by the index decoder 46. A gate 36 operating under control of a multiplexer controller 44 controls this dual-use of the hit line 18 in dependence upon a selected mode of operation. In some embodiments a fast block transfer may be performed by loading data from a first address A into the cache memory 22. A match for the TAG value of the first address A could then be performed and the corresponding hit signal asserted and latched within a latch 43.

Abstract: An S-R flip-flop circuit is provided using two stacks of gates 2, 6 with an internal signal Int stored therebetween. Feedback from the output O is used to switch the state of the internal signal Int in a manner that provides an edge-triggered response for at least one of the inputs.

Abstract: A cache memory 18 is formed of a content addressable memory 20 and a cache RAM 22. The content addressable memory 20 is divided into two or more sections by an AND gate array 28 that serves to selectively either block or unblock the bit lines 26 that supply an input data word to the bit storage and comparison cells 34 of the content addressable memory 20. The generation of match signals for each section is also selectively blocked by preventing the match signal discharge to ground. The match signals from a blocked section are not passed to the RAM 22. The AND gate array 28 and match signal disable may be controlled by the least significant bit of the input data word, higher order bits of the input data word or may be controlled by a bit selected by program control from among the bits of the input data word.

Abstract: A self-timed data processing circuit and method of operation of such a circuit are disclosed. The circuit comprises a plurality of components, such as memory cells, arranged to generate substantially simultaneously a plurality of first output signals, each representing variable data bits. A timed circuit, which may include a plurality of sense amplifiers, is then arranged to receive the first output signals and to generate second output signals for use in subsequent data processing operations, the information content of the second output signals being dependent on the data bits represented by the first output signals. A subset of the components, such as memory cells storing dirty and valid bits for a cache memory, are arranged to generate first output signals representing data bits that are coded so as to cause at least one of the second output signals generated by the timed circuit to transition from its state prior to the generation of the first output signals.

Abstract: A data processing system incorporating a cache memory 2 and a central processing unit. A storage control circuit 10 is responsive to a programmable partition setting PartVal to partition the cache memory between instruction words and data words in dependence upon whether the central processing unit 4 indicates with signal I/D whether the word to be stored within the cache memory 2 resulted from an instruction word cache miss or data word cache miss. The cache memory array 2 may have a programmably sized portion locked down so that it is not replaced. The selection within the complementary programmable range where overwriting takes place uses a pseudo random selection technique using pseudo random number generator in the form of a linear feedback shift register triggering incrementing of a counter.