Patents by Inventor Michael Todd Berens
Michael Todd Berens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984904Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.Type: GrantFiled: May 4, 2022Date of Patent: May 14, 2024Assignee: NXP B.V.Inventor: Michael Todd Berens
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Patent number: 11979169Abstract: A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.Type: GrantFiled: July 14, 2022Date of Patent: May 7, 2024Assignee: NXP USA, Inc.Inventors: Yizhong Zhang, Stefano Pietri, Jie Jin, Michael Todd Berens
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Patent number: 11979151Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.Type: GrantFiled: September 20, 2022Date of Patent: May 7, 2024Assignee: NXP USA, Inc.Inventors: Khoi Mai, Michael Todd Berens, Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Publication number: 20240097686Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Khoi Mai, Michael Todd Berens, Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Publication number: 20230361780Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.Type: ApplicationFiled: May 4, 2022Publication date: November 9, 2023Inventor: Michael Todd Berens
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Publication number: 20230066987Abstract: A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH.Type: ApplicationFiled: August 11, 2022Publication date: March 2, 2023Inventors: Yizhong Zhang, Jie Jin, Stefano Pietri, Michael Todd Berens, Hongyan Yao, Jiawei Fu
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Patent number: 11588495Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.Type: GrantFiled: July 12, 2021Date of Patent: February 21, 2023Assignee: NXP USA, Inc.Inventors: Stefano Pietri, Michael Todd Berens, Yikun Mo, Ashutosh Jain
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Publication number: 20230031469Abstract: A digital to analog converter (DAC) includes an amplifier including a buffer of the DAC, and a resistor ladder arrangement coupled to a non-inverting input terminal of the amplifier to generate a voltage based on a digital control word. The arrangement includes a first, least-significant bit, segment arranged in one of an R-2R or unit-R configuration, a second, most-significant bit, segment including one or more units each including a second-segment-resistor having a resistor terminal coupled to a respective second switch and having a second resistance, RMSB, and a third segment including one or more third-segment-resistors coupled in parallel to the non-inverting input terminal and connected to a first reference voltage terminal. M2 designates a number of bits in the digital control word for controlling the second switches, and the third segment has a total resistance, Rsp, based on M2.Type: ApplicationFiled: July 14, 2022Publication date: February 2, 2023Inventors: Yizhong Zhang, Stefano Pietri, Jie Jin, Michael Todd Berens
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Patent number: 11424754Abstract: Testing of the noise-shaping circuitry within a successive approximation register (“SAR”) analog-to-digital converter (“ADC”) (“SAR ADC”) to ensure it will function as expected, while also providing a method for calibrating the coefficients of the noise-shaping circuitry. Programmable/trimmable circuit component(s) can be used to calibrate the coefficient(s) of the SAR ADC. Digital logic within the SAR engine enables it to selectively skip portions of the ADC conversion process and to use voltage references rather than an analog voltage input signal in sample mode during such test/calibration modes.Type: GrantFiled: May 24, 2021Date of Patent: August 23, 2022Assignee: NXP B.V.Inventor: Michael Todd Berens
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Publication number: 20220052707Abstract: During a sampling phase, an analog front end circuit connects input of a first sampling capacitor to an analog input signal and input of a second sampling capacitor to a reference signal, and connects first and second hold capacitors to ground. During a partial tracking phase, input of the first sampling capacitor is connected to the reference voltage and the input of the second sampling capacitor is connected to the analog input signal. The first hold capacitor is connected to a first output of a gain amplifier and the second hold capacitor to a second output of the gain amplifier. Output of the first sampling capacitor is coupled to a first input of an amplifier and output of the second sampling capacitor is coupled to a second input of the amplifier.Type: ApplicationFiled: July 12, 2021Publication date: February 17, 2022Inventors: Stefano Pietri, Michael Todd Berens, Yikun Mo, Ashutosh Jain
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Patent number: 10790848Abstract: A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.Type: GrantFiled: January 1, 2019Date of Patent: September 29, 2020Assignee: NXP USA, Inc.Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
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Patent number: 10784886Abstract: A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.Type: GrantFiled: February 21, 2020Date of Patent: September 22, 2020Assignee: NXP USA, Inc.Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
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Publication number: 20190372586Abstract: A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.Type: ApplicationFiled: January 1, 2019Publication date: December 5, 2019Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
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Patent number: 10295572Abstract: A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.Type: GrantFiled: April 12, 2018Date of Patent: May 21, 2019Assignee: NXP USA, INC.Inventors: Khoi Mai, Michael Todd Berens, Jon Scott Choy
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Patent number: 10243577Abstract: An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage.Type: GrantFiled: April 2, 2018Date of Patent: March 26, 2019Assignee: NXP USA, Inc.Inventors: Michael Todd Berens, Khoi Mai, James Robert Feddeler
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Patent number: 10110244Abstract: A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.Type: GrantFiled: December 7, 2017Date of Patent: October 23, 2018Assignee: NXP USA, Inc.Inventors: Stefano Pietri, James Robert Feddeler, Michael Todd Berens, Yizhong Zhang
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Patent number: 7733191Abstract: Oscillator devices and methods of operating such oscillator devices are disclosed. The oscillator devices include a current source, and an oscillation module to provide a clock signal. The frequency of the clock signal depends on the relationship between a threshold voltage of a transistor at the oscillation module and the current level provided by the current source. The transistor at the oscillation module is matched to a transistor at the current source so that the frequency of the clock signal is relatively insensitive to changes in device temperature.Type: GrantFiled: February 28, 2007Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Alfredo Olmos, Jefferson Daniel De Barros Soldera, Gang Qian, Michael Todd Berens
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Publication number: 20080204155Abstract: Oscillator devices and methods of operating such oscillator devices are disclosed. The oscillator devices include a current source, and an oscillation module to provide a clock signal. The frequency of the clock signal depends on the relationship between a threshold voltage of a transistor at the oscillation module and the current level provided by the current source. The transistor at the oscillation module is matched to a transistor at the current source so that the frequency of the clock signal is relatively insensitive to changes in device temperature.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Alfredo Olmos, Jefferson Daniel De Barros Soldera, Michael Todd Berens