Patents by Inventor Michael V. Aquilino
Michael V. Aquilino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971625Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.Type: GrantFiled: June 30, 2019Date of Patent: April 6, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Michael V Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, Haiting Wang, Kavya Sree Duggimpudi, Wang Zheng
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Publication number: 20200411689Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.Type: ApplicationFiled: June 30, 2019Publication date: December 31, 2020Inventors: MICHAEL V. AQUILINO, DANIEL JAEGER, MAN GU, BRADLEY MORGENFELD, HAITING WANG, KAVYA SREE DUGGIMPUDI, WANG ZHENG
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Patent number: 10453751Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.Type: GrantFiled: February 14, 2017Date of Patent: October 22, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Xiaofeng Qiu, Michael V. Aquilino, Patrick D. Carpenter, Jessica Dechene, Ming Hao Tang, Haigou Huang, Huy Cao
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Patent number: 10177154Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.Type: GrantFiled: August 30, 2017Date of Patent: January 8, 2019Assignee: International Business Machines CorporationInventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
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Publication number: 20180261510Abstract: A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.Type: ApplicationFiled: February 14, 2017Publication date: September 13, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Xiaofeng QIU, Michael V. AQUILINO, Patrick D. CARPENTER, Jessica DECHENE, Ming Hao TANG, Haigou HUANG, Huy CAO
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Patent number: 10049985Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.Type: GrantFiled: September 8, 2017Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
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Publication number: 20170373007Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.Type: ApplicationFiled: September 8, 2017Publication date: December 28, 2017Inventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
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Publication number: 20170365606Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.Type: ApplicationFiled: August 30, 2017Publication date: December 21, 2017Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
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Publication number: 20170330834Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Inventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
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Patent number: 9818741Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.Type: GrantFiled: June 30, 2015Date of Patent: November 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
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Patent number: 9812400Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.Type: GrantFiled: May 13, 2016Date of Patent: November 7, 2017Assignee: GLOBALFOUNDRIES INCInventors: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino
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Publication number: 20170005098Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Michael V. Aquilino, Veeraraghavan S. Basker, Kangguo Cheng, Gregory Costrini, Ali Khakifirooz, Byeong Y. Kim, William L. Nicoll, Ravikumar Ramachandran, Reinaldo A. Vega, Hanfei Wang, Xinhui Wang
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Patent number: 9035430Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: GrantFiled: August 29, 2012Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Reinaldo A. Vega, Michael V. Aquilino, Daniel J. Jaeger
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Patent number: 8969163Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.Type: GrantFiled: July 24, 2012Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Michael V. Aquilino, Byeong Yeol Kim, Ying Li, Carl John Radens
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Publication number: 20150044843Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: ApplicationFiled: September 18, 2014Publication date: February 12, 2015Inventors: Michael V. Aquilino, Daniel J. Jaeger, Reinaldo A. Vega
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Patent number: 8859388Abstract: A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.Type: GrantFiled: July 13, 2012Date of Patent: October 14, 2014Assignees: International Business Machines Corporation, GLOBALFOUNDRIES Inc.Inventors: Michael V. Aquilino, Xiang Hu, Daniel J. Jaeger, Byeong Y. Kim, Yong M. Lee, Ying Li, Reinaldo A. Vega
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Patent number: 8853796Abstract: A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.Type: GrantFiled: May 19, 2011Date of Patent: October 7, 2014Assignees: GLOBALFOUNDIERS Singapore Pte. Ltd.Inventors: Young Way Teh, Michael V. Aquilino, Arifuzzaman (Arif) Sheikh, Yun Ling Tan, Hao Zhang, Deleep R. Nair, Jinghong H. (John) Li
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Patent number: 8704310Abstract: A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.Type: GrantFiled: February 5, 2013Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Michael V. Aquilino, Reinaldo A. Vega
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Publication number: 20140061862Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: Reinaldo A. VEGA, Michael V. AQUILINO, Daniel J. JAEGER
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Publication number: 20140027820Abstract: A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael V. Aquilino, Byeong Yeol Kim, Ying Li, Carl John Radens