Abstract: Pin placement legality is verified in real-time in a background to reduce a number of input/output assignment analysis runs during a physical design of a programmable logic device. Edited pin properties are checked quickly in the background against certain rules, and results displayed to a user usually before a new pin is edited. Available and legal positions are found and displayed for a selected pin to reduce errors.

Abstract: A graphical tool assists a user in migrating programming changes from one programmable logic device to another. The tool preferably compares a new user configuration dataset (e.g., the user configuration dataset including old features as well as newly-added features) for the “origin” programmable logic device to the existing user configuration dataset (i.e., the user configuration dataset including only old features) for a “destination” programmable logic device, and displays differences to the user. The tool preferably also assists the user to synchronize the devices by “copying” the new features of the user configuration dataset for one device into the old user configuration dataset for another device to the extent possible, by providing graphical inputs to allow the user to indicate which features should be synchronized, or to graphically manipulate the feature assignments directly.