Abstract: A probe card assembly can include an electrical interface to a test system for testing electronic devices such as semiconductor dies. The probe card assembly can also include probes located at a first side of the probe card assembly. The probes, which can be electrically connected to the electrical interface, can be configured to contact terminals of the electronic devices in the test system while the probe card assembly is attached to the test system. The probe card assembly can be configured to impede thermal flow from the probe card assembly to the test system at places of physical contact between the probe card assembly and the test system while the probe card assembly is attached to the test system.

Abstract: A test system can include contact elements for making electrical connections with test points of a DUT. The test system can also include a DC test resource and a signal router, which can be configured to switch a DC channel from the DC test resource between individual contact elements in a group of contact elements.

Abstract: A process or apparatus for testing a plurality of semiconductor dies on a semiconductor wafer utilizing a tester configured to test the dies in groups can include controlling as a logical whole provision of first test signals through a plurality of first communications channels to first probes organized into a plurality of N first probe die groups each configured to contact a different one of the dies of the wafer. One of the first communications channels can be a first common communications channel connected to probes in X of the N first probe die groups but not to probes in Y of the N first probe die groups. X can be at least two and Y can be at least one. The process can also include controlling as a logical whole provision of second test signals through a plurality of second communications channels to second probes organized into a plurality of second probe die groups each configured to contact a different one of the dies of the wafer.

Abstract: A process or apparatus for testing a plurality of semiconductor dies on a semiconductor wafer utilizing a tester configured to test the dies in groups can include controlling as a logical whole provision of first test signals through a plurality of first communications channels to first probes organized into a plurality of N first probe die groups each configured to contact a different one of the dies of the wafer. One of the first communications channels can be a first common communications channel connected to probes in X of the N first probe die groups but not to probes in Y of the N first probe die groups. X can be at least two and Y can be at least one. The process can also include controlling as a logical whole provision of second test signals through a plurality of second communications channels to second probes organized into a plurality of second probe die groups each configured to contact a different one of the dies of the wafer.

Abstract: A test system can include contact elements for making electrical connections with test points of a DUT. The test system can also include a DC test resource and a signal router, which can be configured to switch a DC channel from the DC test resource between individual contact elements in a group of contact elements.

Abstract: A probe card assembly can include an electrical interface to a test system for testing electronic devices such as semiconductor dies. The probe card assembly can also include probes located at a first side of the probe card assembly. The probes, which can be electrically connected to the electrical interface, can be configured to contact terminals of the electronic devices in the test system while the probe card assembly is attached to the test system. The probe card assembly can be configured to impede thermal flow from the probe card assembly to the test system at places of physical contact between the probe card assembly and the test system while the probe card assembly is attached to the test system.