Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract: An apparatus for launching an object in a fluid environment having a tubular member with a forward muzzle end, an opposed rearward end. The object is positioned in the tubular member. Ends of the tubular member are closed by expellable members. Flood valves are located on the expellable members and, on activation, allow flooding of the tubular member by external fluid. A propellant device and an object contact member are disposed within the tubular member. When the propellant device is activated, the object contact member moves the object. These actions are controlled by a control device which first causes the flood valves to enable fluid to flood the interior region. Next, the control device causes the expellable members to be expelled from the tubular member. The control device then causes the propellant device to generate gas in a predetermined manner launching the object from the tubular member.

Abstract: An apparatus for launching an object in a fluid environment having a tubular member with a forward muzzle end, an opposed rearward end. The object is positioned in the tubular member. Ends of the tubular member are closed by expellable members. Flood valves are located on the expellable members and, on activation, allow flooding of the tubular member by external fluid. A propellant device and an object contact member are disposed within the tubular member. When the propellant device is activated, the object contact member moves the object. These actions are controlled by a control device which first causes the flood valves to enable fluid to flood the interior region. Next, the control device causes the expellable members to be expelled from the tubular member. The control device then causes the propellant device to generate gas in a predetermined manner launching the object from the tubular member.

Abstract: A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract: A memory system and a method for controlling power states of a memory device, or a portion thereof, are provided. The memory system includes memory devices, such as DRAMs, a memory controller, chip select lines, and logic for detecting chip select signals from the chip select lines. Each memory device, or a portion therein, is connected to the memory controller by a chip select line. Each chip select line allows the transmission of a chip select signal to a corresponding memory device, or a corresponding portion of the memory device, to select the corresponding memory device, or a portion thereof, to receive commands. Logic is provided to detect the chip select signal. When the logic detects a chip select signal provided to a corresponding memory device, or a portion thereof, that is in a power state lower than its idle state, the memory device, or a portion thereof, is automatically moved from the lower power state to a higher power state.

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Abstract: A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable the data trigger scheme to work in a more heavily loaded configuration where there is more timing skew.

Abstract: A technique to track flag transitions to ensure proper timing of data transfers to and from DRAM devices. In one scheme, a queue is employed to track occurrences of read/write commands, chip select signal and flag transitions to generate a trigger signal to effect the data transfer. In another scheme, read/write command indications are replaced by a rank select signal to enable this data trigger scheme to work even in heavily loaded configurations where there is more timing skew.

Abstract: Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least one buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

Abstract: A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device.

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

Abstract: A computer-implemented system and method for evaluating gas generator launchers is provided. The method includes fixing the system geometry and establishing initial conditions of the launcher to be evaluated. The initial conditions include a mass, composition and geometry of the fuel included in the gas generant, geometries of the system components, initial pressures and temperatures and the mass and geometry of the device to be launched. A gas generator internal ballistics burn rate is modeled and an amount of mass and energy added to the combustion chamber as the fuel is consumed is calculated. Then, using conservation of mass and energy principles, an energy flux rate is modeled, beginning with the fuel and ending with the work performed on the device in order to propel it from the launcher.

Abstract: A memory system includes a plurality of memory device ranks. A memory controller having a connection with the plurality of memory device ranks is adapted to obtain command information being issued to one of the plurality of memory device ranks. The memory controller is also adapted to generate a power weight value based on a command type from the command information. The memory controller increments a power count of the one of the plurality of memory device ranks by the power weight value generated. The memory controller then compares the power count of the one of the plurality of memory device ranks to a threshold value set for the one of the plurality of memory device ranks. If it is determined that the power count exceeds the threshold value, the memory controller is adapted to throttle the one of the plurality of memory device ranks.

Abstract: A memory controller to generate refresh requests for by storing the status of memory rows and an arithmetic logic unit to store a second status of all the memory rows of all the memory devices in the system memory configuration. A second logic unit stores the open status of the plurality of memory banks. The third logic generates a refresh request based on the open status and the second status in response to a refresh frequency.

Abstract: A method of handling memory read return data from different time domains includes determining a number of distinct memory device ranks. A time domain for each of the distinct memory device ranks is determined. A transaction is scheduled based on the time domain for each of the distinct memory device ranks so that at least one of data collisions and out-of-order data returns are prevented.

Abstract: A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

Abstract: A memory interface scheme reduces propagation delay by utilizing source-synchronous signaling to transmit address/command information to memory devices. A memory module in accordance with the present invention may include an address/command buffer that samples address/command information responsive to an address/command strobe signal and then passes the address/command information to a memory device on the module. A retiming circuit may be used to control the timing of read-return data from a memory device on the module.