Abstract: Apparatus for switching data to a bus including apparatus for driving a bus to a first data receiving condition during a first clock period, apparatus for driving the bus to a second data awaiting condition during a second clock period, apparatus for releasing the bus from the second data awaiting condition during the second clock period, and apparatus for maintaining the bus in the second data awaiting condition.

Abstract: A digital phase lock loop circuit for synchronizing the phase of clock signals delivered to devices through clock tree circuitry with the phase of input clock signals including a first delay line, a second delay line, a phase detector circuit, apparatus for transferring the input clock signals through the first delay line to the phase detector circuit, apparatus for transferring the input clock signals through the second delay line and the clock tree circuitry to the phase detector circuit, apparatus responsive to the difference in phase detected between the clock signals transferred through the first and second delay lines for varying the delay of one of the delay lines to bring the clock signals transferred through the first and second delay lines into phase with one another.