Patents by Inventor Michael Zernack

Michael Zernack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305095
    Abstract: A semiconductor wafer having a plurality of die is attached to a support structure. The semiconductor wafer includes an active layer over a silicon layer, wherein the active layer is at a top side, and a bottom side exposes the silicon layer. While the wafer is attached to the support structure, an infrared laser beam is focused through a portion of the silicon layer to create a modification region along saw lanes located between neighboring die of the plurality of die. Afterwards, a metal layer is formed on the exposed silicon layer at the bottom side of the semiconductor wafer. The metal layer is attached to an expansion tape, and the wafer is singulated by extending the expansion tape to separate the die of the plurality of die along the saw lane. A first singulated die of the plurality of die is packaged to form a packaged semiconductor device.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Sascha Moeller, Guido Albermann, Michael Zernack
  • Patent number: 10347534
    Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP B.V.
    Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
  • Publication number: 20190080963
    Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 14, 2019
    Inventors: Martin LAPKE, Hartmut Buenning, Sascha MOELLER, Guido ALBERMANN, Michael ZERNACK, Leo M. HIGGINS, III
  • Patent number: 8895363
    Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 25, 2014
    Assignee: NXP B.V.
    Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack
  • Publication number: 20140264768
    Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: NXP B. V.
    Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Michael Zernack