Patents by Inventor Michael Zimin
Michael Zimin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146053Abstract: A resonance avoidance system including a resonance avoidance controller configured to insert a delay between sequential transactions on a communication interface separated by an inactive period to avoid stimulating a power distribution network resonance. The resonance avoidance controller may be configured to insert the delay by delaying a second transaction from being driven onto the communication interface after a first transaction in which the delay is sufficient to avoid stimulating the power distribution network resonance. The delay may be inserted by delaying a driver from driving the second transaction by the sufficient delay. The conflict may be detected between first and second commands in a command queue, in which the delay may be inserted by inserting no operation commands between the commands in the command queue. Operational timing values may be stored that are used to detect resonant frequency conflicts.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Joshua Siegel, James Andrew Welker, Michael Zimin
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Patent number: 11169952Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.Type: GrantFiled: April 14, 2020Date of Patent: November 9, 2021Assignee: NXP B.V.Inventors: Jan-Peter Schat, Ling Wang, Michael Zimin
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Publication number: 20200341937Abstract: The disclosure relates to a data transmission interface for use in a first integrated circuit (IC) for encoding and sending a data packet from the first IC to a second IC via a data bus having four data wires, the data transmission interface arranged to generate four time-dependent binary signals which jointly encode the data packet in signal edges thereof, each of the signals being associated with a unique wire of the data bus and spanning a temporal cycle T within which are defined four consecutive time stamps T1 . . . T4 at which edges can occur in the signals, the data transmission interface further arranged to transmit the signals to the second IC substantially in parallel on their respective data wires, wherein: irrespective of the data packet content, at each time stamp T1 . . . T4 at least one of the four signals has an edge to enable clock recovery at the second IC.Type: ApplicationFiled: April 14, 2020Publication date: October 29, 2020Inventors: Jan-Peter Schat, Ling Wang, Michael Zimin
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Patent number: 8060770Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.Type: GrantFiled: November 2, 2005Date of Patent: November 15, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Dan Kuzmin, Michael Priel, Michael Zimin
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Patent number: 8018247Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.Type: GrantFiled: November 30, 2004Date of Patent: September 13, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Michael Priel, Dan Kuzmin, Michael Zimin
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Patent number: 7741826Abstract: A method and a device, the device has ground voltage elevation compensation capabilities and includes: multiple current consuming components; a positive voltage supply input; a negative voltage supply input; and a compensation circuit, coupled to the negative voltage supply input and to a grounding element; wherein the compensation circuit is adapted to detect a ground voltage elevation resulting from a flow of excess consumption current through the grounding element, and in response couple the negative voltage supply input to the grounding element; wherein the excess current flows through the grounding element due to an increment in a current consumption of a current consuming element of the device.Type: GrantFiled: August 13, 2007Date of Patent: June 22, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Yefim Fefer, Michael Zimin, Sergey Sofer
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Patent number: 7573762Abstract: A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance, timing characteristics and an operating mode. A set of one time programmable elements can be used to selectively store information for modifying operating parameters and replacing the defective memory cells with redundant memory cells.Type: GrantFiled: June 6, 2007Date of Patent: August 11, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Prashant U. Kenkare, Michael Zimin
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Publication number: 20090003114Abstract: A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit.Type: ApplicationFiled: November 30, 2004Publication date: January 1, 2009Applicant: Freescale Semiconductor, Inc.Inventors: Michael Priel, Dan Kuzmin, Michael Zimin
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Publication number: 20080304347Abstract: A system with a repairable memory array having redundant memory cells to replace one or more defective memory cells that are detected after fabrication. The system also includes non memory array circuits having circuitry that may adjust one or more operating parameters such as operating current, operating voltage, resistance, capacitance, timing characteristics and an operating mode. A set of one time programmable elements can be used to selectively store information for modifying operating parameters and replacing the defective memory cells with redundant memory cells.Type: ApplicationFiled: June 6, 2007Publication date: December 11, 2008Inventors: Prashant U. Kenkare, Michael Zimin
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Publication number: 20080294927Abstract: A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.Type: ApplicationFiled: November 2, 2005Publication date: November 27, 2008Applicant: Freescale Semiconductor, Inc.Inventors: Dan Kuzmin, Michael Priel, Michael Zimin