Abstract: A process for producing multi-chip wiring arrangements which consist of a ceramic carrier with through contact holes associated with thin film wiring on one side of the carrier and with multi layer, thick layer wiring on the other side of the carrier. The holes on the one side of the carrier are metallized and galvanically strengthened while the holes on the other side of the carrier are sealed by baking therein a thick layer of paste. Thereafter the multi layer, thick layer wiring and the thin film wiring are produced in that order.

Abstract: A process for producing multi-chip wiring which facilitates high packing density and reliable flip-chip connections. In the process, an adhesive layer and a contact layer are vapor deposited onto a carrier. The desired structure of the connector path, outer contacts and connection surfaces are covered with a conductive layer and an intermediate layer with the aid of a first photo-lacquer mask by galvanic metal deposition. A solder-rejecting layer is galvanically deposited onto the structure of the conductor paths with the aid of a second photo-lacquer mask. The undesired regions of the adhesive layer and of the contact layer are etched away and the outer contacts and connection surfaces are covered with a solderable contact layer by selective currentless metal deposition.