Patents by Inventor Michal Schramm
Michal Schramm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9825587Abstract: An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.Type: GrantFiled: July 21, 2016Date of Patent: November 21, 2017Assignee: NUVOTON TECHNOLOGY CORPORATIONInventors: Yuval Kirschner, Nimrod Peled, Michal Schramm, Victor Adrian Flachs, Ofer Cohen
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Patent number: 8688944Abstract: An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.Type: GrantFiled: September 20, 2011Date of Patent: April 1, 2014Assignee: Nuvoton Technology CorporationInventors: Moshe Alon, Michal Schramm, Nir Tasher
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Patent number: 8543755Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.Type: GrantFiled: January 29, 2012Date of Patent: September 24, 2013Assignee: Nuvoton Technology CorporationInventors: Moshe Alon, Ilia Stolov, Erez Naory, Nir Tasher, Yuval Kirschner, Michal Schramm
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Publication number: 20130073810Abstract: An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: NUVOTON TECHNOLOGY CORPORATIONInventors: Moshe Alon, Michal Schramm, Nir Tasher
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Patent number: 8375234Abstract: Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power.Type: GrantFiled: February 19, 2008Date of Patent: February 12, 2013Assignee: Winbond Electronics CorporationInventors: Michal Schramm, Ziv Hershman, Yehezkel Friedman, Zeev Heller
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Patent number: 8285895Abstract: A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.Type: GrantFiled: August 6, 2007Date of Patent: October 9, 2012Assignee: Winbond Electronics CorporationInventors: Michal Schramm, Nir Tasher
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Publication number: 20120239848Abstract: An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.Type: ApplicationFiled: January 29, 2012Publication date: September 20, 2012Applicant: NUVOTON TECHNOLOGY CORPORATIONInventors: Moshe Alon, Ilia Stolov, Erez Naory, Nir Tasher, Yuval Kirschner, Michal Schramm
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Patent number: 7890726Abstract: An apparatus and method are disclosed. The apparatus allows dynamic setting of access permissions to contents of a shared memory in a memory device controlled by an embedded controller and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via an arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the shared memory.Type: GrantFiled: August 22, 2007Date of Patent: February 15, 2011Assignee: Winbond Electronics CorporationInventors: Ohad Falik, Michal Schramm
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Patent number: 7676003Abstract: A method for processing a signal envelope generated by demodulating a received signal that includes a train of pulses that is transmitted at a carrier frequency and is modulated at a given baud rate with data symbols in accordance with a predetermined communication protocol, which defines features of the modulated signal. The method includes measuring a duration of a selected feature in the signal envelope as defined by the communication protocol. The baud rate of the signal is estimated based on the measured duration without counting the pulses in the received signal. The data symbols are decoded by processing the signal envelope responsively to the estimated baud rate.Type: GrantFiled: September 6, 2006Date of Patent: March 9, 2010Assignee: Winbond Electronics CorporationInventors: Victor Flachs, Michal Schramm, Leonid Shamis
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Publication number: 20090210734Abstract: Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power.Type: ApplicationFiled: February 19, 2008Publication date: August 20, 2009Applicant: WINBOND ELECTRONICS CORPORATIONInventors: Michal Schramm, Ziv Hershman, Yehezkel Friedman, Zeev Heller
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Patent number: 7508257Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.Type: GrantFiled: September 6, 2006Date of Patent: March 24, 2009Assignee: Winbond Electronics CorporationInventors: Victor Flachs, Michal Schramm, Ilan Margalit
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Publication number: 20090043916Abstract: A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.Type: ApplicationFiled: August 6, 2007Publication date: February 12, 2009Applicant: Winbond Electronics CorporationInventors: Michal Schramm, Nir Tasher
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Publication number: 20080075471Abstract: Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.Type: ApplicationFiled: September 6, 2006Publication date: March 27, 2008Applicant: WINBOND ELECTRONICS CORPORATIONInventors: Victor Flachs, Michal Schramm, Ilan Margalit
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Publication number: 20080056411Abstract: A method for processing a signal envelope generated by demodulating a received signal that includes a train of pulses that is transmitted at a carrier frequency and is modulated at a given baud rate with data symbols in accordance with a predetermined communication protocol, which defines features of the modulated signal. The method includes measuring a duration of a selected feature in the signal envelope as defined by the communication protocol. The baud rate of the signal is estimated based on the measured duration without counting the pulses in the received signal. The data symbols are decoded by processing the signal envelope responsively to the estimated baud rate.Type: ApplicationFiled: September 6, 2006Publication date: March 6, 2008Applicant: WINBOND ELECTRONICS CORPORATIONInventors: Victor Flachs, Michal Schramm, Leonid Shamis
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Patent number: 7318129Abstract: An apparatus and method are disclosed for protecting the contents of a shared memory in a memory device controlled by an embedded controller. The apparatus allows dynamic setting of access permissions to said contents and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. An arbitration device for allocating access paths to the memory device is also provided. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory.Type: GrantFiled: December 12, 2005Date of Patent: January 8, 2008Assignee: Winbound Electronics CorporationInventors: Ohad Falik, Michal Schramm
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Patent number: 6976136Abstract: An apparatus and method are disclosed for protecting the contents of a shared memory in a memory device controlled by an embedded controller. The apparatus allows dynamic setting of access permissions to said contents and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. An arbitration device for allocating access paths to the memory device is also provided. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory.Type: GrantFiled: May 7, 2001Date of Patent: December 13, 2005Assignee: National Semiconductor CorporationInventors: Ohad Falik, Michal Schramm
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Publication number: 20020166061Abstract: An apparatus and method are disclosed for protecting the contents of a shared memory in a memory device controlled by an embedded controller. The apparatus allows dynamic setting of access permissions to said contents and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. An arbitration device for allocating access paths to the memory device is also provided. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory.Type: ApplicationFiled: May 7, 2001Publication date: November 7, 2002Inventors: Ohad Falik, Michal Schramm