Abstract: A method of tracking a user's toothcare activity comprises receiving video images of a user's face during, e.g. a toothbrushing session, and identifying, in each of a plurality of frames of the video images, predetermined features of the user's face. The features include at least two invariant landmarks associated with the user's face and one or more landmarks selected from at least mouth feature positions and eye feature positions. Predetermined marker features of a toothcare appliance, e.g. a brush in use are identified in each of the plurality of frames of the video images. From the at least two invariant landmarks associated with the user's nose, a measure of inter-landmark distance is determined. An appliance length normalised by the inter-landmark distance is determined. From the one or more landmarks selected from at least mouth feature positions and eye feature positions, one or more appliance-to-facial feature distances each normalised by the inter-landmark distance is determined.

Abstract: A method is disclosed for determining with computing apparatus an adequate number of clusters for summarizing result data that includes a large number of observation data points. The summary data includes a small number of samples of data from each cluster with the number of clusters being large enough to provide a good summary of all the result data without being so large as to make it difficult for one skilled in the art to examine visually all of the summary data generated by the computing apparatus.

Abstract: A computing device is described that executes a centralized service and a plurality of applications. The centralized service detects a change from a first power mode of the computing device to a second power mode of the computing device and responsive to detecting the change, determines a first application from the plurality of applications executing at the computing device, to notify of the change from the first power mode to a second power mode. The centralized service outputs to the first application an indication of the change from the first power mode to the second power mode, and responsive to receiving an indication response from the first application, suspends an application processor of the computing device.

Abstract: A visual advertisement is disclosed which is carried by a substrate. The advertisement comprises a first inverse perspective transformation image and a contiguous second inverse perspective transformation image. The images are inverted with respect to one another. The first image, when the images are viewed in one direction, is the predominant image and the second image is a subsidiary image. When the images are viewed in the opposite direction the second image is the predominant image and the first image is the subsidiary image.

Abstract: A method is disclosed for determining with computing apparatus an adequate number of clusters for summarizing result data that includes a large number of observation data points. The summary data includes a small number of samples of data from each cluster with the number of clusters being large enough to provide a good summary of all the result data without being so large as to make it difficult for one skilled in the art to examine visually all of the summary data generated by the computing apparatus.

Abstract: A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.

Abstract: A method and apparatus is disclosed for compilation of an original Cobol program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a two stage compilation process, the first compilation/translation step by a first specialized compiler/translator that takes as input a Cobol source program that includes parallelization directives, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives in the second computer programming language. The intermediate program is then compiled utilizing a selected second compiler that provides support for parallelism described in the second programming language. The approach optionally allows for use of pragmas serving as parallelization directives to the compiler in the original Cobol program or in the intermediate program.

Abstract: A method and apparatus is disclosed for compilation of an original Cobol program and building an executable program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a compilation (or translation) step utilizing a first compiler or translating program which is a parallel aware translating first compiler. The parallel aware first compiler is a specialized compiler/translator which takes as input a Cobol source program, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives, the intermediate program intended for further compilation utilizing an existing selected second compiler, the second compiler providing support for parallelism for programs described in the second programming language.

Abstract: A method and apparatus is disclosed for compilation of an original Cobol program and building an executable program with support for improved performance by increased parallelism during execution using multiple threads of processing. The approach includes a compilation (or translation) step utilizing a first compiler or translating program which is a parallel aware translating first compiler. The parallel aware first compiler is a specialized compiler/translator which takes as input a Cobol source program, and produces as output an intermediate computer program in a second computer programming language, the intermediate program including parallelization directives, the intermediate program intended for further compilation utilizing an existing selected second compiler, the second compiler providing support for parallelism for programs described in the second programming language.

Abstract: This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

Abstract: A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache memory or processor module, with each chain containing processes ready for dispatch. The dispatcher checks the queues in priority order, starting with the priority chain for a queue, followed by the chain corresponding to the cache memory or processor module that the process last executed upon, followed by chains corresponding to other cache memories or processor modules.