Abstract: A coder-decoder device for OQPSK signals with four phase states comprises a coder for converting a binary signal bit stream T.sub.n into two digital bit streams X.sub.n and Y.sub.n and a decoder for restoring the digital bit stream T.sub.n from the digital bit streams X.sub.n and Y.sub.n applied to its inputs. The coder comprises a first logic circuit for assigning to each bit of the bit stream X.sub.n the binary value 1 or 0 in accordance with the logic equationX.sub.n =(T.sub.n *+H.sub.n /2)*.sym.X.sub.n-1where H.sub.n /2 designates synchronization pulses in phase with the bits of the bit stream T.sub.n. A second logic circuit assigns to each bit of the bit stream Y.sub.n the binary value 1 or 0 in accordance with the logic equationY.sub.n =T.sub.n .sym.X.sub.n .sym.X.sub.n-1 .sym.Y.sub.n-1.The decoder comprises a third logic circuit which assigns to each bit of the restored bit stream T.sub.n the binary value in accordance with the following logic equation:T.sub.n =X.sub.n .sym.X.sub.n-1 .sym.Y.sub.n .sym.

Abstract: An amplifier for correcting group time delay of electrical signals comprises first and second DC voltage supply terminals, an input transistor to which a signal to be amplified is applied, an output transistor, a group time delay corrector network, at least one capacitor and a choke. The input and output transistors have their respective collector-emitter junctions connected in series between the first and second supply terminals. They are configured as common-emitter voltage amplifiers. The collector of the input transistor is connected to the base of the output transistor through the group time delay corrector network. The emitter of the output transistor is connected to one of the supply terminals through the capacitor and to the collector of the input transistor through the choke.