Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.

Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

Abstract: A method includes generation of a first current proportional to absolute temperature and formation of a second current representative of the temperature variation of the threshold voltages of the transistors of the inverter and limited to a fraction of the first current. This fraction is less than one. The inverter is supplied with a supply current equal to the first current minus the limited second current.

Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature.

Abstract: An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency.

Abstract: A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage).

Abstract: A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawtooth voltage generator has a first discharge capacitor and a second discharge capacitor that are alternately discharged with a feedback control sink current from a high voltage reference voltage level. The output signals of the two sawtooth voltage generators are compared to control a phase frequency comparator that provides signals to control a dual charge pump that provides the feedback control source current and that provides the feedback control sink current.

Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is a logarithmic function, where each has a mathematical correlation to a function of the power supply voltage.

Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Abstract: A voltage level shifter is disclosed that includes low voltage devices. In some implementations, a voltage level shifter having a differential structure includes low voltage, complementary N-channel metal oxide semiconductor (NMOS) input transistors and low voltage, complementary cross-coupled P-channel metal oxide semiconductor (PMOS) output transistors. One or more complementary NMOS/PMOS series intermediate transistor pairs are interposed between respective drains of the NMOS transistors and PMOS transistors to limit high voltage drops across the NMOS input transistors and PMOS output transistors. In some implementations, each intermediate transistor pair is biased by a single intermediate voltage. The sources of the low voltage devices are connect to a bulk/substrate. The complementary outputs of the level shifter can be taken from the drains of the NMOS/PMOS series intermediate transistor pairs.

Abstract: An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency.

Abstract: This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature.

Abstract: A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a comparator output signal to a phase frequency comparator, the output of which controls a source of the variable feedback control current. A method includes controlling the amplitude of a sawtooth output signal by charging a capacitor in a sawtooth voltage generator with a variable feedback control current; comparing a version of the sawtooth output signal with a fixed reference voltage to provide a comparator output signal; processing the comparator output signal in a phase frequency comparator to provide up/down control signals; and controlling the variable feedback control current with the up/down control signals from the phase frequency comparator.

Abstract: An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements.

Abstract: A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC.