Abstract: An association memory which permits the execution of all kinds of comparative operations. The associative memory includes a memory map (1) in which a search argument, which has been processed in a scanning module (3) and a masking unit (5,7), is compared to the data stored in the memory. After this comparison, the data obtained is recorded in a response register (11). When the search data and the stored data supply an association of variable length words, the result data is processed in a module for the processing of variable-length words (13) and in a multiple-response management module.

Abstract: The invention relates to a memory cell for a static associative memory comprising two arrays of transistors, a first array having a data storage function and a second array having a comparison function between the stored data item and a data item applied to the input of the cell, the comparison result being obtained on a selection line S, in which the second array (T1,T2,T3,T4) of transistors is partly formed by the transistors of the first array (T3,T4,T7,T8,T5,T6). The structure of the cell thus has reduced overall dimensions compared with known structures.

Abstract: A circuit which performs a linear transformation on a digital signal. A linear transformation is defined by a graph whose nodes represent operations of addition or subtraction and the branches operations of multiplication by a determined coefficient. According to the invention, the circuit comprises a multiplier for each branch, this multiplier being wired according to the value of the determined coefficient of said branch, and an adder for each node, each adder being wired according to the nature of the operation, addition or subtraction, associated with said node.

Abstract: Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B.