Abstract: In order to have the functional modules of a local unit communicate with one another and with an external bus, the device embodying the invention comprises: at least one internal bus of the same type as the external bus per functional module, the latter being coupled to the internal busses so that each module is the sole transmitter on at least one of the internal busses and is a receiver on the other internal busses; an additional internal bus for each external bus of the same type as said internal busses, ensuring the dissemination to the functional modules of data transiting on the external bus; and a coupling module ensuring transfer towards the external bus of the data circulating on the internal busses and destined for another local unit connected to the external bus.

Abstract: The device embodying the invention uses at least two read-only memory blocks containing the instructions of the application code and of which the addressing inputs are respectively connected to two counters connected to the address bus of the microprocessor. The read outputs of these blocks are connected to the data bus of the microprocessor via two buffers. A control circuit is provided to control, as a function of the nature of the addresses transmitted on the address bus and at the rhythm of the latter, a succession of cycles each comprising the transfer on the data bus, via one or other of the buffers, of the data contained in one or other of the memories and the incrementing of the counter associated with the other memory, in order to anticipate the data transfer of the next cycle. The invention applies notably to the processors taken on board aerodynes.

Abstract: The method embodying the invention comprises management by a coprocessor of the time slicing, from a pre-established frame, of the processing cycle of the processor, into slices of possibly different durations, of the allocation of the time slices to the different functions installed according to one or plural pre-established layouts, of the saving at the end of the machine context slice of the function being processed, this with a view to resuming this function during the following slice associated with it and of the loading, at the start of a new slice, of the machine context linked with the activating of the function associated with this slice and which was previously saved at the end of a previous slice corresponding to this function. The invention applies to the optimizing and security of real-time management in modular avionics architectures.

Abstract: A device for enhancing the performance of a real time executive kernel associated with a multiprocessor structure possibly comprising a large number of processors comprises a real time operator behaving, as seen from the processor of the structure, like a memory area. The real time operator sends and receives data to be processed, generates communication control signals and manages the real time context of the processors of the structure. It comprises a plurality of identical hardwired real time operator circuits accessible simultaneously by the processors of the structure but each associated with one only of said processors. The device can be used even if the structure comprises a large number of processors.