Abstract: Apparatus and methods for conversion from signed integer to a floating point representation are provided. Two's complementation and lead zero count operations are performed in parallel. Exponent generation and mantissa shifting are performed in parallel. Generation of the floating point exponent from the signed integer, including application of a scaling factor, is performed using a 3:2 compressor or carry-save adder and an adder. Two's complementation for generation of the mantissa in unsigned integer format is performed using an adder. Lead zero count for controlling mantissa shifting is performed by one's complementing the signed integer if negative, counting lead zeros in the one's complement output, and determining, using the one's complement output, whether the one's complement lead zero count differs from the two's complement lead zero count by one.

Abstract: A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

Abstract: A method comprises receiving an N-bit unsigned number and a control signal, in response to the control signal indicating an increment operation, increasing the N-bit unsigned number by 1 through an increment/decrement apparatus having (2m+3) levels of 2-input logic gates, wherein m is equal to log2(N) and in response to the control signal indicating a decrement operation, decreasing the N-bit unsigned number by 1 through the increment/decrement apparatus.

Abstract: Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.

Abstract: A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

Abstract: A method comprises receiving an N-bit unsigned number and a control signal, in response to the control signal indicating an increment operation, increasing the N-bit unsigned number by 1 through an increment/decrement apparatus having (2m+3) levels of 2-input logic gates, wherein m is equal to log2(N) and in response to the control signal indicating a decrement operation, decreasing the N-bit unsigned number by 1 through the increment/decrement apparatus.

Abstract: Apparatus and methods for conversion from signed integer to a floating point representation are provided. Two's complementation and lead zero count operations are performed in parallel. Exponent generation and mantissa shifting are performed in parallel. Generation of the floating point exponent from the signed integer, including application of a scaling factor, is performed using a 3:2 compressor or carry-save adder and an adder. Two's complementation for generation of the mantissa in unsigned integer format is performed using an adder. Lead zero count for controlling mantissa shifting is performed by one's complementing the signed integer if negative, counting lead zeros in the one's complement output, and determining, using the one's complement output, whether the one's complement lead zero count differs from the two's complement lead zero count by one.

Abstract: An adder and a method for calculating a sum of three input operands. The adder comprises a pre-processor, a generator and a post-processor. The pre-processor creates an initial propagation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry in bit is propagated as a carry out bit as determined from a value of respective bit-positions of each of the three operands. The pre-processor creates an initial generation vector having a plurality of bit-positions, each bit-position in the plurality representing whether a carry out bit is generated as determined from a value of respective bit-positions of each of the three operands. The generator generates a composite propagation vector and a composite generation vector from parallel prefix operations on the initial propagation vector and initial generation vector. The post-processor calculates the sum from the initial propagation vector, the composite propagation vector and the composite generation vector.

Abstract: Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.