Abstract: In this system STM (Synchronous Transfer Mode) and ATM (Asynchronous Transfer Mode) cell streams are supplied to corresponding STM and ATM switching exchanges STME and ATME via the cascade connection of a multiplexer (MUX), a transmission link (LI) and a demultiplexer (DMUX). The MUX and DMUX are each constituted by a switching element with a plurality of inputs (II/2; I3) and outputs (03, 04/5) coupled to a common switching means (SB1, TM1; SB2, TM2) via respective receiver (RC1/3) and transmitter (TC1/3) circuits. The common switching means samples the input cell streams at a frequency at least equal to the sum of the time slot frequencies of the time frames of the input cell streams. The time frames of the input and output cell streams are phase synchronous and the sampling of the input cell streams is performed in a predetermined order. The cells of the resultant (STM/ATM) cell stream are supplied to the transmitter circuits in function of their destination.

Abstract: Packet switching network with first and second cascaded parts, including first and second switching modules respectively. In the second switching modules, the path selection is controlled by routing information contained in the packets. In the first switching modules this selection is performed without using routing information only for a path set-up packet, while for the following packets use is made of routing information on the route followed by the path set-up packet. Each module decides to multiplex an input stream on an output only when a calculated traffic load is smaller than a limit value. This load is calculated from traffic load parameters contained in the path set-up packet.

Abstract: A switching system using an asynchronous packet switching technique is provided wherein the packets may contain voice, data or video signals. The switching speed is increased through the use of a processor analyzing only specified packets, said processor being located out of the transmission path of the packets. The processor may process the specified packets at a lower speed than the transmission speed of the switching system. A header correction circuit is used to improve the quality of the transmission.