Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.

Abstract: By appropriate arrangement of two sets of tables chosen to be complementary, cells which are conveyed through a first multiplexor, n RAM storages and the second are subject to a cell rearrange-ment enabling introduction of at least one bitmap field, thereby producing the n Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage, one particular byte is stored into one RAM available for a Write operation by use of the first set of tables, thereby causing an alteration to the normal association between the n RAMs and the n Logical Units which is then re-established by the second set of tables.

Abstract: A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell.

Abstract: The present invention describes direct decoding of Error Correction Codes (ECC) such as, for example, FIRE and similar codes, and detecting and correcting errors occurring in burst, without requiring any pattern shift or sequential logic. According to the present invention, the syndrome of a code generated with a degree-d polynomial is split into sub-syndromes that are combined to form at least one kind of error pattern from which an error pattern is picked. If the picked error pattern does not correspond to an uncorrectable error and errors are not confined within first d bits, one of the sub-syndromes is selected according to the correction mode. The ranks of this selected sub-syndrome and picked error pattern in the Galois field generated by a factor of the degree-d polynomial are determined.

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract: A single check field can be generated and appended to packets prior to a switching or other operation to support post-operation verification that protected fields were not altered during the operation and that the post-operation packet sequence matches the pre-operation packet sequence. The check field requires the use of nominally-synchronized packet counters at the check field generating system and at the verification system. The check field is generated by performing a CRC calculation on the protected fields of the packet. The CRC result is combined with the current packet count to obtain the final check field, which is appended to the packet. At the verification system, a CRC calculation is performed on the protected fields of the packet, included the appended final check field. This provides an interim check result which is compared to the current packet count at the verification system. A non-null compare result is indicative of an error condition.

Abstract: A fault tolerant switching architecture is provided with two separate switch fabrics each having a switch cure located in a centralized building and a set of SCAL elements distributed in different physical areas. Each SCAL element has both a SCAL receive element and a SCAL transmit element for access to a corresponding input and output port of the swatch core. A set of port adapters is distributed at different physical areas, with each connected switch fabrics via a particular SCAL element so that each switch core receives the sequence of cells coming from any port adapter and conversely any port adapter may receive cells from either one of the switch cores. Each switch fabric can detect an internal breakdown condition occurring in one of its element and send an error control signal to the peer element located in the other switch fabric.

Abstract: An ATM protocol adapter designed to operate with high speed switching systems having a receive and transmit elements based upon pipeline structure insuring that each operation is performed in a limited period.

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering.

Abstract: A protocol adapter for an Asynchronous Transfer Mode (ATM) cell switching system has a receive part and a transmit part, the receive part being arranged to convert an incoming ATM cell into a cell structured with a payload and a header including an output index (OI). The transmit part is arranged to convert the structured cell after it is routed through the switching system into an ATM cell, and to output the ATM cell on the ATM communication lines. The transmit part has cell processing logic for adding a bit (mother-bit) in the header of each incoming structured The output index of a mother cell is used to access a location in a look-up table which contains for each output index, a multicast bit for indicating whether the cell is to be multicasted or not, a queue index for indicating a location where to enqueue the cell before it is outputted from the transmit part, a new VP/VC/Li value for constructing a new header, and a next-output index.

Abstract: A cell switching module and switching system for routing cells each having a cell header comprising a plurality of input and output ports; at least one common cell storage connected between the input and output ports and comprising a plurality of storage locations having addresses; a storage section for performing storage of cells coming through any one of the input ports into the common cell storage and comprising a plurality of receiver means for performing the physical interface for the plurality of input ports, a plurality of input routers for connection the input ports to the cell storage, a plurality of ASA registers for providing the input routers with addresses to be used for storing the cells into the cell storage; and a retrieve section for retrieving cells from storage and for transporting them to one of the output ports, where the retrieve section comprises a plurality of output routers for retrieving the data stored in any locations of the cell storage, a plurality of drivers for connecting to th

Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part.

Abstract: An interface and protocol for linking devices (18) with a control unit (10). The interface includes a dedicated request line (30) per device, a dot-ORed acknowledge line (32), at least one clock line (38) transmitting sets of N clock pulses from the control unit to a device during each data exchange, two data line (34, 36) for serial duplex data transmission and a pair of shift registers one being positioned in the control unit and another being positioned in each of the devices. The protocol is such that for either a read or a write operation the control unit issues two request signals in spaced relationship on the request line and the selected device responds with two acknowledge signals is spaced relationship on the acknowledge line with each one of the acknowledge signals falling after the fall of its associated request signal.

Abstract: An error detection apparatus is implemented in a passive device inserted on a synchronous bus, linking two devices. The bus has data lines onto which data are transferred between the two devices under control of tag lines and clock signals which are companion of the transferred data. The apparatus allows errors to be detected, the failing device to be identified and the error signals to be reported in a psuedo-synchronous way on an error bus due to error detection and reporting logic circuits and a pseudo-synchronous timing circuit.