Abstract: Disclosed is a system and method for eliminating the unnecessary toggling of logic in a logic network. The method and system can be incorporated directly into logic synthesis software, or may be implemented manually. Provided is a mechanism for identifying critical nets and then inserting net latches at the critical nets wherein each net latch is controlled by an enable signal that also controls a related output latch. Each net latch is comprised of a circuit which can on command hold static the last logic level on a given logic node.

Abstract: A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.

Abstract: An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Abstract: An operational amplifier with two differential input stages is used to separately achieve low offset voltage and broad bandwidth characteristics. One input stage addresses dc and low frequency signals while the other addresses broadband frequencies. All transistors forming the dc stage are biased in the sub-threshold region. Following the two differential input stages, the signal paths are recombined in a capacitive cross-over network that provides outputs for subsequent amplification. The cross over frequency is adjustable from 15 kHz to 50 kHz using small practical values for the cross-over capacitor. The gain balance between the two input stages is adjustable by resistors and/or predetermined width/length ratios of the operational amplifier transistors.

Abstract: A matrix of thermal sensors is provided for accurately evaluating the thermal characteristics of an integrated circuit. The integrated circuit is evenly divided into a plurality of sectors in which a thermal comparison to a known thermal mass will be performed. Each sector includes at least one dual cell comprising a local thermal sensor for providing an output corresponding to a local temperature of the integrated circuit in that sector, and a background thermal sensor. The outputs of selective ones of the background thermal sensors are combined to provide a signal corresponding to a background temperature of the integrated circuit. A decoder/enabler arrangement is used to selectively gate the output of a specific local thermal sensor in a sector to a difference circuit where it is compared to the collective output of selected ones of the background sensors to generate a thermal measurement of the sector under test.

Abstract: A compound cascode amplifier comprising first and second FET input transistors, the gates of which are coupled to a differential input, and first and second FET cascode transistors. The sources of the first and second cascode transistors are coupled respectively to the drains of the first and second input transistors. The gate of the first cascode transistor is coupled to a reference voltage V Ref. The drain of the first cascode transistor is coupled to the gate of the second cascode transistor, and the drain of the second cascode transistor forms the output of the circuit. In operation the drive to the gate of the second cascode transistor arrives in synchronization with the drive to the source thereof, such that the drive to the gate arrives in anticipation of a voltage swing at the output of the second cascode transistor amplifier, not in reaction to it. Accordingly, this arrangement does not introduce a delay or an additional pole in the frequency response of the circuit.

Abstract: An NTL (Non-Threshold Logic) NOR logic circuit exhibits a small signal swing, effected by establishing a pseudo threshold level by utilizing a low voltage power supply and a combination of NPN bipolar devices arranged to provide an essentially noise immune circuit having high DC gain and high AC noise tolerance.

Abstract: A logic circuit has a plurality of serially connected logic units wherein each unit is a gate comprising a resistor serially connected to a combination of a plurality of transistors connected together in parallel. The transistors of the logic circuit are arranged to enable reduction of the requisite voltage to be provided by an external power source. By reduction of the voltage, the values of resistance can be reduced without exceeding a power dissipation budget. Alternate logic units, in a series of logic units, are constructed of PNP and NPN transistors. Furthermore, the voltage drop across a transistor of a preceding logic unit, as measured between the emitter and collector terminals of a transistor, is applied, essentially, across the base-emitter junction of a transistor in a succeeding logic unit so as to provide a supply of base current to the transistor of the succeeding logic unit without danger of saturating the transistor and without cutting off current flow to the transistor.

Abstract: A semiconductor memory cell for selectively storing or outputting differential signals responsive to a SELECT signal supplied on a word line includes: a transistor pair having cross-coupled base-collector terminals and emitter terminals connected to a common reference potential; a sensing circuit connected to each of the base-collector terminals in the transistor pair, each of the sensing circuits including (a) a first diode having a cathode connected to the base-collector terminal, (b) a second diode having an anode connected to the anode of the first diode and a cathode connected to the word line, and (c) a circuit connected at the commonly connected anodes of the first and second diodes for amplifying the signal thereat; a writing circuit connected to each of the transistors in the transistor pair, the writing circuit including a transistor having a base connected to the word line and a collector connected to the base-collector terminal; and a circuit for supplying constant current to each of the base-coll

Abstract: A half current switch comprising: at least one input transistor, a load resistance connected between a first voltage reference and the collector of the input transistor, a constant-current resistance connected between the emitter of the input transistor and a second voltage reference, and a feedback means including at least one feedback connected to the constant-current resistance. The feedback means further includes means for biasing the feedback transistor to drive a current through the constant current resistance which, when flowing, increases with an increasing main current and decreases with a decreasing main current through the input transistor. The feedback means thus causes a constant current to be drawn by the input transistor when it is conducting, thereby controlling the capacitance of the input transistor while maintaining the output level constant.

Abstract: An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.

Abstract: A method and apparatus for applying focus correction to an E-beam or charged particle system to compensate for wafer warp and mask tilt. In an electron beam system including a registration system which measures the position of four registration marks with the beam and calculates the apparent magnification error of a given chip, means are also provided for using magnification and rotation error information to calculate a height error factor and to apply a compensating current to a dynamic focusing coil of the electron beam to move the effective beam focal plane to a position which matches the wafer or mask plane at each chip site.