Patents by Inventor Michele Alessandro Carrano

Michele Alessandro Carrano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11803226
    Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 31, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta′, Sergio Abenda
  • Publication number: 20230318590
    Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.
    Type: Application
    Filed: March 21, 2023
    Publication date: October 5, 2023
    Inventors: Riccardo Condorelli, Michele Alessandro Carrano, Antonino Mondello
  • Publication number: 20230291538
    Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 14, 2023
    Inventors: Riccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano
  • Patent number: 11742757
    Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: August 29, 2023
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l.
    Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
  • Publication number: 20230213578
    Abstract: A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 6, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Riccardo CONDORELLI, Antonino MONDELLO, Michele Alessandro CARRANO
  • Publication number: 20230090664
    Abstract: The present disclosure relates to a method including executing, by an electronic device, a first firmware module stored in a volatile memory of the electronic device, the execution of the first firmware module causing an updated firmware key to be stored in a non-volatile memory of the electronic device, and uploading a second firmware module to the electronic device. The method also includes decrypting the second firmware module by a cryptographic processor of the electronic device based on the updated firmware key, and installing the decrypted second firmware module in the volatile memory of the electronic device at least partially overwriting the first firmware module.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 23, 2023
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonino MONDELLO, Michele Alessandro CARRANO, Riccardo CONDORELLI
  • Publication number: 20220271663
    Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
  • Patent number: 11283353
    Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 22, 2022
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ALPS) SAS
    Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
  • Publication number: 20210357015
    Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
    Type: Application
    Filed: May 14, 2020
    Publication date: November 18, 2021
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta', Sergio Abenda
  • Publication number: 20190319538
    Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
  • Patent number: 10236066
    Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 19, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Roberto Sebastiano Ruggirello
  • Publication number: 20180240523
    Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.
    Type: Application
    Filed: August 31, 2017
    Publication date: August 23, 2018
    Inventors: Daniele MANGANO, Michele Alessandro CARRANO, Gaetano DI STEFANO, Roberto Sebastiano RUGGIRELLO
  • Patent number: 9823965
    Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 21, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Antonin Fried
  • Publication number: 20170068594
    Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.
    Type: Application
    Filed: March 24, 2016
    Publication date: March 9, 2017
    Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Distefano, Antonin Fried
  • Patent number: 8390346
    Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: March 5, 2013
    Assignee: STMicroelectronics, SRL
    Inventors: Riccardo Condorelli, Michele Alessandro Carrano
  • Publication number: 20110221498
    Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.
    Type: Application
    Filed: February 18, 2011
    Publication date: September 15, 2011
    Applicant: STMicroelectronics S.r.l.
    Inventors: Riccardo CONDORELLI, Michele Alessandro CARRANO