Patents by Inventor Michele Alessandro Carrano
Michele Alessandro Carrano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11803226Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.Type: GrantFiled: May 14, 2020Date of Patent: October 31, 2023Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta′, Sergio Abenda
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Publication number: 20230318590Abstract: In accordance with an embodiment, a method includes: producing a set of delayed replicas of a reference clock signal, wherein delayed replicas in the set of delayed replicas have respective signal edges delayed in time by a mutual time delay therebetween; producing a set of edge detecting signals comprising edge detecting signals indicative of respective distances of edges of delayed replicas in the set of delayed replicas from an edge of a clock signal having a clock period; selecting based on edge detecting signals in the set of edge detecting signals a delayed replica in the set of delayed replicas having a distance from the clock signal edge that is shorter than the distance from the clock signal edge of any other delayed replica in the set of delayed replicas.Type: ApplicationFiled: March 21, 2023Publication date: October 5, 2023Inventors: Riccardo Condorelli, Michele Alessandro Carrano, Antonino Mondello
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Publication number: 20230291538Abstract: A method includes providing a reference clock signal having a reference period, providing a sampling clock signal having a sampling clock period shorter than the reference period of the reference clock signal, measuring the first subperiod as a first ratio of the first subperiod to the period of the sampling clock signal, measuring the second subperiod as a second ratio of the second subperiod to the period of the sampling clock signal, detecting a starting edge of a clock signal having a clock period greater than the reference period, producing a reconstructed reference signal based on the first ratio, the second ratio, and the detected starting edge, comparing the clock period of the clock signal with a period of the reconstructed reference signal to obtain a differential signal indicating a difference therebetween, and providing the differential signal to user circuitry for calibrating the clock signal.Type: ApplicationFiled: February 24, 2023Publication date: September 14, 2023Inventors: Riccardo Condorelli, Antonino Mondello, Michele Alessandro Carrano
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Patent number: 11742757Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.Type: GrantFiled: February 9, 2022Date of Patent: August 29, 2023Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics S.r.l.Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
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Publication number: 20230213578Abstract: A system-on-chip includes a process-voltage-temperature (PVT) sensor with a filter circuit that initiates a patterned digital signal and propagates the patterned digital signal in a manner responsive to variations in semiconductor material, operating supply voltage and operating temperature of the system-on-chip. A digital comparison circuit compares the initiated patterned digital signal and the propagated patterned digital signal. A warning signal is generated in response to the comparison where there is a detection of discrepancy between the initiated patterned digital signal and the propagated patterned digital signal.Type: ApplicationFiled: December 28, 2022Publication date: July 6, 2023Applicant: STMicroelectronics S.r.l.Inventors: Riccardo CONDORELLI, Antonino MONDELLO, Michele Alessandro CARRANO
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Publication number: 20230090664Abstract: The present disclosure relates to a method including executing, by an electronic device, a first firmware module stored in a volatile memory of the electronic device, the execution of the first firmware module causing an updated firmware key to be stored in a non-volatile memory of the electronic device, and uploading a second firmware module to the electronic device. The method also includes decrypting the second firmware module by a cryptographic processor of the electronic device based on the updated firmware key, and installing the decrypted second firmware module in the volatile memory of the electronic device at least partially overwriting the first firmware module.Type: ApplicationFiled: September 16, 2022Publication date: March 23, 2023Applicant: STMicroelectronics S.r.l.Inventors: Antonino MONDELLO, Michele Alessandro CARRANO, Riccardo CONDORELLI
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Publication number: 20220271663Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.Type: ApplicationFiled: February 9, 2022Publication date: August 25, 2022Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
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Patent number: 11283353Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.Type: GrantFiled: April 16, 2019Date of Patent: March 22, 2022Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ALPS) SASInventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
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Publication number: 20210357015Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Daniele Mangano, Michele Alessandro Carrano, Pasquale Butta', Sergio Abenda
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Publication number: 20190319538Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.Type: ApplicationFiled: April 16, 2019Publication date: October 17, 2019Inventors: Francois Druilhe, Patrik Arno, Alessandro Inglese, Michele Alessandro Carrano
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Patent number: 10236066Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.Type: GrantFiled: August 31, 2017Date of Patent: March 19, 2019Assignee: STMicroelectronics S.r.l.Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Roberto Sebastiano Ruggirello
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Publication number: 20180240523Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.Type: ApplicationFiled: August 31, 2017Publication date: August 23, 2018Inventors: Daniele MANGANO, Michele Alessandro CARRANO, Gaetano DI STEFANO, Roberto Sebastiano RUGGIRELLO
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Patent number: 9823965Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.Type: GrantFiled: March 24, 2016Date of Patent: November 21, 2017Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Di Stefano, Antonin Fried
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Publication number: 20170068594Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.Type: ApplicationFiled: March 24, 2016Publication date: March 9, 2017Inventors: Daniele Mangano, Michele Alessandro Carrano, Gaetano Distefano, Antonin Fried
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Patent number: 8390346Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.Type: GrantFiled: February 18, 2011Date of Patent: March 5, 2013Assignee: STMicroelectronics, SRLInventors: Riccardo Condorelli, Michele Alessandro Carrano
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Publication number: 20110221498Abstract: A system for synchronizing the operation of a circuit with a control signal includes synchronization flip-flops operating in cascade for receiving a control signal to be synchronized and providing a corresponding control signal synchronized with a clock signal, and a circuit including a finite state machine for receiving the clock signal having state flip-flops for storing the current state of the finite state machine, wherein a last synchronization flip-flop includes one of the state flip-flops.Type: ApplicationFiled: February 18, 2011Publication date: September 15, 2011Applicant: STMicroelectronics S.r.l.Inventors: Riccardo CONDORELLI, Michele Alessandro CARRANO