Patents by Inventor Michele De Fazio
Michele De Fazio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953967Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: GrantFiled: April 26, 2023Date of Patent: April 9, 2024Assignee: Apple Inc.Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Publication number: 20230333625Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: ApplicationFiled: April 26, 2023Publication date: October 19, 2023Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Patent number: 11669145Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: GrantFiled: September 15, 2021Date of Patent: June 6, 2023Assignee: Apple Inc.Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Publication number: 20230080624Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.Type: ApplicationFiled: September 15, 2021Publication date: March 16, 2023Inventors: Shawn Searles, Preethi Damodaran, Ofir Gilad, Michele De Fazio, Inder M. Sodhi, Enrico Zanetti, Olivier Girard, Lothar Münch, Andrea Barsanti, Andrea Lazzeri
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Patent number: 11428717Abstract: A current measurement circuit is disclosed. The current measurement circuit includes first and second circuit branches coupled to a circuit node through which current is to be measured. During a first period, the first circuit branch converts the current into a first voltage. During a second period, the second circuit branch converter the current into a second voltage. An analog-to-digital converter is configured to convert the first and second voltages into digital values indicative of the measured current. A control circuit is configured to alternately select one of the first and second branches during the generation of the digital values.Type: GrantFiled: September 25, 2020Date of Patent: August 30, 2022Assignee: Apple Inc.Inventors: Michele De Fazio, Shawn Searles
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Publication number: 20220099712Abstract: A current measurement circuit is disclosed. The current measurement circuit includes first and second circuit branches coupled to a circuit node through which current is to be measured. During a first period, the first circuit branch converts the current into a first voltage. During a second period, the second circuit branch converter the current into a second voltage. An analog-to-digital converter is configured to convert the first and second voltages into digital values indicative of the measured current. A control circuit is configured to alternately select one of the first and second branches during the generation of the digital values.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Inventors: Michele De Fazio, Shawn Searles
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Patent number: 10355595Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.Type: GrantFiled: October 22, 2018Date of Patent: July 16, 2019Assignee: Dialog Semiconductor (UK) LimitedInventors: Mark Childs, Tiago Patrao, Pietro Gallina, Alexandre Tavares, Michele De Fazio
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Publication number: 20190058399Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Mark Childs, Tiago Patrao, Pietro Gallina, Alexandre Tavares, Michele De Fazio
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Patent number: 10110126Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.Type: GrantFiled: September 4, 2015Date of Patent: October 23, 2018Assignee: Dailog Semiconductor (UK) LimitedInventors: Mark Childs, Tiago Patrao, Pietro Gallina, Alexandre Tavares, Michele De Fazio
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Publication number: 20170070145Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.Type: ApplicationFiled: September 4, 2015Publication date: March 9, 2017Inventors: Mark Childs, Tiago Patrao, Pietro Gallina, Alexandre Tavares, Michele De Fazio
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Publication number: 20160169947Abstract: A measurement circuit for providing the maximum and/or minimum voltage of a time-variant electrical input signal is presented. The measurement circuit contains a voltage reference unit to provide voltage reference signals and a comparator unit comprising multiple comparators. Each comparator receiving the electrical input signal at a first comparator input and a different voltage reference signal from the voltage reference unit at its second comparator input. The comparator unit provides comparator output signals based on said electrical input signal and said voltage reference signals. A logic unit receives the comparator output signals and provides a voltage output signal indicative of the maximum and/or minimum voltage of the electrical input signal based on the comparator output signals. The logic unit provides adaptation information to the voltage reference entity. The is adaptation information is dependent on the comparator output signals.Type: ApplicationFiled: December 10, 2015Publication date: June 16, 2016Inventors: Michele De Fazio, Andrea Acquas, Fabio Rigoni
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Patent number: 7372313Abstract: A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance and are controllable by a plurality of control signals different from one another and configured in such a way as to obtain a total impedance between said first and second terminals that is substantially variable in a continuous manner.Type: GrantFiled: July 11, 2006Date of Patent: May 13, 2008Assignee: STMicroelectronics S.r.l.Inventors: Michele De Fazio, Felice Alberto Torrisi
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Publication number: 20070018709Abstract: A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance and are controllable by a plurality of control signals different from one another and configured in such a way as to obtain a total impedance between said first and second terminals that is substantially variable in a continuous manner.Type: ApplicationFiled: July 11, 2006Publication date: January 25, 2007Applicant: STMicroelectronics S.r.l.Inventors: Michele De Fazio, Felice Torrisi