Abstract: A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.

Abstract: A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.

Abstract: A bond pad structure and method are provided. The structure includes a first conductive layer formed over a substrate. A second conductive layer is formed over a first portion of the first conductive layer, and a first portion of the second conductive layer forms a first capacitor electrode. A third conductive layer is formed over the first conductive layer and second conductive layer, and a first portion of the third conductive layer forms a second capacitor electrode. A second portion of the third conductive layer forms a wire bond region. A dielectric material is disposed between the first capacitor electrode and the second capacitor electrode to form a first capacitor.

Abstract: A die crack detector and method are provided. A first metal trace is formed over a substrate with the first metal trace configured to extend around a perimeter of a semiconductor die. A second metal trace is formed over the first metal trace with the second metal trace configured to overlap the first metal trace. A dielectric material is disposed between the first and second metal traces. A first detector terminal is coupled to the first metal trace and a second detector terminal coupled to the second metal trace. The detector terminals are configured to receive a predetermined voltage.

Abstract: A die crack detector and method are provided. A first metal trace is formed over a substrate with the first metal trace configured to extend around a perimeter of a semiconductor die. A second metal trace is formed over the first metal trace with the second metal trace configured to overlap the first metal trace. A dielectric material is disposed between the first and second metal traces. A first detector terminal is coupled to the first metal trace and a second detector terminal coupled to the second metal trace. The detector terminals are configured to receive a predetermined voltage.

Abstract: Methods and systems for achieving semiconductor-based circuits or systems having multiple components with one or more matched or similar characteristics or features are disclosed herein. In one example embodiment, a system includes a processing device that includes first, second, and third circuitry. The first circuitry is configured to generate control signals that at least indirectly cause a pick and place head mechanism to attempt to pick up and place at least some of first and second dice. The second circuitry is configured to assess whether attempts to implement one or more of first and second dice should be skipped based upon wafer map information. Further, the third circuitry is configured to determine whether a second position of a first one of the second dice is sufficiently proximate to a first position so that it would be appropriate to implement the first one of the second dice.