Patents by Inventor Michelle L Wong

Michelle L Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7610431
    Abstract: In an interconnect apparatus for interconnecting at least one host to at least a plurality of presentation registers provide a presentation interface for the device to the host. The interconnect apparatus includes memory for holding the presentation registers and a governor operable to manage the presentation registers in the memory.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: October 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: John Watkins, Ola Tørudbakken, John Petry, Michelle L Wong, Ravinandan R Buchamwandla
  • Patent number: 6148372
    Abstract: A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously. The cache includes a first non-blocking cache receiving data access requests from a device in a processor, and a first miss queue storing entries corresponding to data access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided and receives data access requests from the first miss queue, and a second miss queue stores entries corresponding to data access requests not serviced by the second non-blocking cache. A first arbiter arbitrates between two or more access requests to the first non-blocking cache. A second arbiter can be provided to arbitrate between two or more access requests to the second non-blocking cache.The arbiter is capable of determining if an anticipatory stall signal should be asserted if any of the cache resources, such as a queuing structure, is becoming overloaded.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: November 14, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Sharad Mehrotra, Michelle L. Wong
  • Patent number: 6145054
    Abstract: A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: November 7, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Sharad Mehrotra, Ricky C. Hetherington, Michelle L. Wong