Patents by Inventor Michie Sunayama
Michie Sunayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9559058Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.Type: GrantFiled: March 29, 2012Date of Patent: January 31, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
-
Patent number: 8497208Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: GrantFiled: September 16, 2010Date of Patent: July 30, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
-
Publication number: 20120181695Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.Type: ApplicationFiled: March 29, 2012Publication date: July 19, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA
-
Patent number: 8168532Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.Type: GrantFiled: November 10, 2008Date of Patent: May 1, 2012Assignee: Fujitsu LimitedInventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
-
Patent number: 8119524Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.Type: GrantFiled: December 14, 2010Date of Patent: February 21, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Noriyoshi Shimizu
-
Patent number: 8067836Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.Type: GrantFiled: April 29, 2009Date of Patent: November 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masaki Haneda, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Michie Sunayama, Takahiro Tabira
-
Patent number: 8003527Abstract: A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.Type: GrantFiled: July 26, 2010Date of Patent: August 23, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Noriyoshi Shimizu
-
Patent number: 8003518Abstract: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.Type: GrantFiled: September 24, 2009Date of Patent: August 23, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masaki Haneda, Noriyoshi Shimizu, Michie Sunayama
-
Publication number: 20110151661Abstract: A first film containing a first metal material having a diffusion preventing function for copper, a second film containing oxygen-contained copper film, a third film containing copper and a second metal material which exhibits a diffusion preventing function for copper by bonding with oxygen, and a fourth film of copper as the main material are formed in an opening formed in an insulating film, and then a barrier layer containing the first metal material, the second metal material and oxygen is formed by thermal processing between the insulating film and the fourth film.Type: ApplicationFiled: December 14, 2010Publication date: June 23, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Michie Sunayama, Noriyoshi Shimizu
-
Patent number: 7955970Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.Type: GrantFiled: July 9, 2009Date of Patent: June 7, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
-
Publication number: 20110034026Abstract: A semiconductor device manufacturing method includes forming an interlayer dielectric film above a semiconductor substrate; forming a first wiring trench with a first width and a second wiring trench with a second width that is larger than the first width inr the interlayer dielectric film; forming a first seed layer that includes a first additional element in the first wiring trench and the second wiring trench; forming a first copper layer over the first seed layer; removing the first copper layer and the first seed layer in the second wiring trench while leaving the first copper layer and the first seed layer in the first wiring trench; forming a second seed layer in the second wiring trench after removing the first copper layer and the first seed layer in the second wiring trench; and forming a second copper layer over the second seed layer.Type: ApplicationFiled: July 26, 2010Publication date: February 10, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Michie Sunayama, Noriyoshi Shimizu
-
Publication number: 20110003475Abstract: A method for producing a semiconductor device including a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
-
Patent number: 7816279Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: GrantFiled: February 11, 2009Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Yoshiyuki Nakao, Noriyoshi Shimizu
-
Patent number: 7803642Abstract: A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment.Type: GrantFiled: August 27, 2009Date of Patent: September 28, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
-
Publication number: 20100009530Abstract: A semiconductor device fabrication method including the steps of: forming an interlayer insulating film on a substrate; forming an opening in the interlayer insulating film; forming an alloy layer containing manganese and copper to cover the inner surface of the opening; forming a first copper layer of a material containing primarily copper on the alloy layer to fill the opening; forming, on the first copper layer, a second copper layer of a material containing primarily copper and a higher concentration of oxygen, carbon or nitrogen than the first copper layer; heating the substrate on which the second copper layer has been formed; and removing the second copper layer.Type: ApplicationFiled: September 24, 2009Publication date: January 14, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masaki Haneda, Noriyoshi Shimizu, Michie Sunayama
-
Publication number: 20090321937Abstract: A semiconductor device includes an insulating film including oxygen formed over a semiconductor substrate, a recess formed in the insulating film, a refractory metal film formed on the inner wall of the recess, a metal film including copper, manganese, and nitrogen formed on the refractory metal film, and a copper film formed on the metal film to fill in the recess.Type: ApplicationFiled: April 29, 2009Publication date: December 31, 2009Applicant: FUJITSU LIMITEDInventors: Masaki HANEDA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Michie SUNAYAMA, Takahiro TABIRA
-
Publication number: 20090317925Abstract: A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment.Type: ApplicationFiled: August 27, 2009Publication date: December 24, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
-
Publication number: 20090269925Abstract: A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring.Type: ApplicationFiled: July 9, 2009Publication date: October 29, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Michie Sunayama, Noriyoshi Shimizu, Masaki Haneda
-
Publication number: 20090200670Abstract: A semiconductor device includes a first conductor disposed on a semiconductor substrate; an oxygen-containing insulation film disposed on the semiconductor substrate and on the first conductor, the insulation film having a contact hole which extends to the first conductor and a trench which is connected to an upper portion of the contact hole; a zirconium oxide film disposed on a side surface of the contact hole and a side surface and a bottom surface of the trench; a zirconium film disposed on the zirconium oxide film inside the contact hole and inside the trench; and a second conductor composed of Cu embedded into the contact hole and into the trench.Type: ApplicationFiled: February 11, 2009Publication date: August 13, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Michie SUNAYAMA, Yoshiyuki NAKAO, Noriyoshi SHIMIZU
-
Publication number: 20090121355Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.Type: ApplicationFiled: November 10, 2008Publication date: May 14, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masaki HANEDA, Michie SUNAYAMA, Noriyoshi SHIMIZU, Nobuyuki OHTSUKA, Yoshiyuki NAKAO, Takahiro TABIRA