Patents by Inventor Michiko Odagiri

Michiko Odagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Batch erasable single chip nonvolatile memory device and erasing method therefor
    Patent number: 5898621
    Abstract: A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvo
    Type: Grant
    Filed: July 31, 1997
    Date of Patent: April 27, 1999
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
  • Batch erasable nonvolatile memory device and erasing method
    Patent number: 5677868
    Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cell
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: October 14, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada
  • Batch erasable nonvolatile memory device and erasing method
    Patent number: 5598368
    Abstract: A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: January 28, 1997
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Masahito Takahashi, Michiko Odagiri, Takeshi Furuno, Kazunori Furusawa, Masashi Wada