Abstract: In a differential amplifier comprising a non-linear distortion compensating circuit including a differential emitter follower, and a first group of current sources having a first differential pair of transistors having bases receiving a pair of emitter currents of the differential emitter follower, respectively, so that the first group of current sources are controlled by the pair of emitter currents of the differential emitter follower, and a differential buffer including a second differential pair of transistors having bases receiving signals outputted from the non-linear distortion compensating circuit, respectively, there is provided a base current compensating circuit for supplying to emitter nodes of the differential emitter follower, a current for reducing a non-linear distortion caused by base currents of the transistors of the second differential pair in the differential buffer and the transistors of the first differential pair in the first group of current sources.

Abstract: An input circuit provided in a semiconductor integrated circuit, comprises an nMOS transistor having a source connected to an input node receiving a transmission signal, a drain connected to a first node and a gate connected to a reference potential, and a pMOS transistor having a source connected to a power supply voltage, a drain connected to the first node, a first inverter having an input connected to the first node and an output connected to an output terminal, and a second inverter having an input connected to the first node and an output connected to a gate of the pMOS transistor, so that when the nMOS transistor is turned on, the pMOS transistor is rendered off, whereby no steady input current flows.

Abstract: A first load 10 is connected between a signal terminal 12 for driving an output transistor 11 and a highest potential VCC. A first switch 7 is connected in parallel with the first load 10. A second switch 8 is connected between the signal terminal 12 and a current source 14. A third switch 9 is connected between the highest potential VCC and the current source 14. The first to third switches are on-off operated according to a CMOS level input to provide an ECL level from an output transistor. The current source 14 includes a bipolar transistor 1 and a resistor 2, thereby occupying only a small area and precluding output fluctuations due to fluctuations in manufacture.

Abstract: In a reference voltage generating circuit, a standardized constant voltage measured on the basis of a low power supply voltage as a reference is generated by a constant voltage source connected between a high power supply voltage and the low power supply voltage. The standardized constant voltage is divided by a series circuit composed of first and second resistors sandwiching first and second transistors therebetween, for generating a divided voltage, which is then supplied to a current source composed of a third transistor. A current flowing through the current source is converted into an output voltage measured on the basis of the high power supply voltage as a reference, by third and fourth resistors series-connected to sandwich the third transistor therebetween. The output voltage is converted, by an emitter follower composed of a fourth transistor having a base receiving the output voltage, into a reference voltage measured on the basis of the high power supply voltage as a reference.

Abstract: In a semiconductor memory device, a data is written in a memory cell through a pair of digit lines during a write operation time interval. An equalizing operation is performed to the pair of digit lines in response to an equalizing control signal during the write operation time interval to recover potentials of the digit lines. In order to suppress output change of a sense amplifier circuit on the equalizing operation, a load of the sense amplifier circuit is changed in response to the equalizing control signal by a flip-flop circuit such that the load becomes heavier than that before the equalizing operation. The flip-flop circuit is composed of a flip-flop section, and first and second transfer gates connected between the outputs of the sense amplifier circuit and the inputs of the flip-flop section. The first and second transfer gates are set to the conductive state in response to the equalizing control signal.

Abstract: In a synchronous semiconductor memory having a memory section (MS) for memorizing a particular datum, a single output latch circuit (32) is connected to an output side of the memory section and controlled by the use of a pulse signal whether or not the particular datum is passed through the output latch circuit. The pulse signal is produced in a pulse generator (31) to synchronize with an internal clock signal which is produced in an internal clock signal producing arrangement (21 and 22). The pulse signal has a pulse width which is independent of the internal clock signal and determined dependent on a timing when the memory section outputs the particular datum.

Abstract: A semiconductor memory circuit comprises a plurality of memory cells each connected to a corresponding word line and a corresponding pair of digit lines connected connected to a sense amplifier. Each pair of digit lines are connected to one pair of read bus lines, which are respectively connected to emitters of a pair of transistors forming a current-voltage converter. The semiconductor memory circuit also includes one buffer which comprises a first bipolar transistor having an emitter connected to one of the pair of read bus lines, and a second bipolar transistor having an emitter connected to the other of the pair of read bus lines. Bases of the first and second bipolar transistors are connected to each other, and emitters of the first and second bipolar transistors are connected to different current sources, respectively. Collectors of the first and second bipolar transistors are connected being respectively connected to the emitters of the pair of transistors of the current-voltage converter.

Abstract: A current mirror constant current source circuit includes a first current mirror circuit constituted by first and second source-grounded n-channel MOS transistors connected to form a current mirror. A source-drain path of the first MOS transistor forms an input current path of the current mirror circuit, and a source-drain path of the second MOS transistor forms an output current path of the current mirror circuit. A current source is connected between a drain of the first MOS transistor and a high voltage supply line. A third n-channel MOS transistor is connected to have a source and a drain connected to a source and a drain of the first MOS transistor, respectively. A gate of the third MOS transistor is connected to the high voltage supply line. The current source includes a second current mirror circuit formed by two MOS transistors such that the source-drain path of one of the two transistors forms an output current path of the second current mirror circuit.