Abstract: A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during ?t1; and the one indicating that the voltage increases from V1 to E during ?t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of ?t1, V1, and ?t2.

Abstract: A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during ?t1; and the one indicating that the voltage increases from V1 to E during ?t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of ?t1, V1, and ?t2.

Abstract: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Abstract: Regions G1 to G8 each including a predetermined number of flip-flops (FF) are divided into two groups. This dividing is performed so that the number of data connection channels intersected by a boundary is minimized. In the case of intersection of two data connection channels (A1, A2), the number of data connection channels intersected by the boundary is two, the minimum number. After grouping of all the regions (G1 to G4, G5 to G8), clock tree synthesis (CTS) is performed. If clock forming is performed in this way, the increase in clock skew on an actual device can be limited and on-chip variation resistance can be increased.

Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Abstract: The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.

Abstract: An automatic-arrangement-wiring apparatus is provided with a calculating unit for calculating the lowest transfer rate and a corresponding repeater-to-repeater distance for each of wiring layers having different time constants, an arrangement unit or carrying out automatic arrangement, an estimating unit for estimating the wire length of each of wiring routes based on arrangement results, another calculating unit for calculating a transfer rate threshold required of each wiring route whose wire length is equal to or longer than a wire length threshold specified by the user from a propagation delay and the estimated wire length, an assigning unit for assigning a wiring layer having the highest transfer rate among selected wiring layers to each wiring route in question, a repeater inserting unit for inserting one or more repeaters into each wiring route in question, and a wiring processing unit for performing automatic wiring.

Abstract: A delay calculation method that is capable of calculating delay time with a small margin of error is provided for delay calculation in a logic circuit. The operating characteristics of transistor are expressed with a fixed resistance and a power supply voltage that changes with time. The power supply voltage is represented as a waveform which is a combination of two straight lines: the one indicating that the voltage, after a fixed delay of t0, increases to V1 during ?t1; and the one indicating that the voltage increases from V1 to E during ?t2 and thereafter remains at the fixed value of E. A difference in the shapes of input waveforms is adopted as a correction parameter to determine the values of ?t1, V1, and ?t2.

Abstract: In accordance with a circuit modification method, when it is determined that an aggressor (2) causes a glitch error in a victim (1), the one or more positions where one or more buffers are to be inserted into the victim (1) are determined based on the coupling capacity Cc between the victim (1) and the aggressor (2). One or more buffers are inserted at one or more internal points of division of the victim (1) which are determined so that the coupling capacity between each of a plurality of wire segments, into which the victim is to be divided by the one or more internal points of division, and the aggressor 2 is equal to Cc/n, where n is the number of wire segments. Furthermore, since the one or more buffers are inserted so that the coupling capacity Cc is properly divided into the coupling capacities between the plurality of wire segments and the aggressor, the amount of glitch to be caused in each of plurality of wire segment can be reduced and no further addition of buffers is needed.

Abstract: A semiconductor integrated circuit includes a test pass and a test circuit that are placed on the way of the test pass so that a stage has the same excess value when the stage has different stage labels and different excess values in a scan chain of a stage interval n. A test pattern generation method for the semiconductor integrated circuit is also disclosed.

Abstract: In the linear filter circuit, a right shift circuit derives A×2−n by shifting the input pixel value A rightward by n bits. A selector selects either the input pixel value A or an input pixel value B according to an n-bit blending factor &agr;, conducts computation of (A×&agr;_+B×&agr;), and outputs n partial products. A Wallace adder adds up a total of (n+1) partial products output from the selector and the right shift circuit, and thereby derives an output value Y=A×(1−&agr;)+B×&agr; of the linear filter circuit.

Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.

Abstract: A wiring data generation method includes the steps of generating a line in a block of a first level, carrying out layout of the block of the first level in a block of a second level higher than the first level, and generating mesh lines of the block of the second level connected to the line in the block of the first level within the block of the second level.

Abstract: A gate delay calculation apparatus includes an Rs parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an Rs determination portion for selectively extracting the parameter prestored in the Rs parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by Rs determination portion and the output load model.

Abstract: A gate delay calculation apparatus includes an Rs parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continues time function, an Rs determination portion for selectively extracting the parameter prestored in the Rs parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by Rs determination portion and the output load model.

Abstract: The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.

Abstract: The operating characteristic of a transistor, modeled by a resistive element having fixed resistance and a power source voltage that varies with time, is segmented into a linearity region in which a current increases as a gate potential varies and a saturation region in which the current gradually decreases as the gate potential remains at a constant level, so that gradual decrease in current in a saturation region of the transistor is properly reflected and a delay time is estimated in a precise manner.

Abstract: In accordance with a circuit modification method, when it is determined that an aggressor (2) causes a glitch error in a victim (1), the one or more positions where one or more buffers are to be inserted into the victim (1) are determined based on the coupling capacity Cc between the victim (1) and the aggressor (2). One or more buffers are inserted at one or more internal points of division of the victim (1) which are determined so that the coupling capacity between each of a plurality of wire segments, into which the victim is to be divided by the one or more internal points of division, and the aggressor 2 is equal to Cc/n, where n is the number of wire segments. Furthermore, since the one or more buffers are inserted so that the coupling capacity Cc is properly divided into the coupling capacities between the plurality of wire segments and the aggressor, the amount of glitch to be caused in each of plurality of wire segment can be reduced and no further addition of buffers is needed.

Abstract: In cases where a delay time in a wire, which connects a first NAND placed on the upstream side and a second NAND placed on the downstream side, is calculated, there are a plurality of logical paths in the first NAND, and a parasitic capacitance of an output pin of the first NAND is determined for each logical path. Therefore, the parasitic capacitance corresponding to each logical path of the first NAND is separated from a fixed load model which indicates a sum of a load of the wire and a capacitance of an input pin of the second NAND, and the parasitic capacitance is added to the fixed load model in the calculation of the delay time. Accordingly, a load for the delay time calculation can be produced while precisely reflecting the parasitic capacitance changing with the logical path on the load production, and the delay time calculation can be performed with high accuracy.

Abstract: In a semiconductor integrated circuit device, a clock buffer is arranged at the center of a chip by using a core I/O technique for arranging an input/output buffer at an arbitrary position. A clock is wired such that, with reference to a wire extending to a circuit in a chip which is farthest from the clock buffer and must be synchronously controlled. Wires extending to the other circuits are intentionally bypassed to make wires extending to all the circuits electrically equal to each other in length. Thus, a skew of a clock can be suppressed due to the isometric wiring.