Patents by Inventor Michio Miyazaki
Michio Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113648Abstract: A motor control apparatus includes: a converter circuit; an inverter circuit; a current detector; a regenerative resistor; a regenerative resistor controller; and a control device. The converter circuit converts alternating current from an alternating current power supply to direct current, converts regenerative direct current from the inverter circuit to regenerative alternating current, and further supplies the regenerative alternating current to the alternating power supply. The inverter circuit converts the direct current to alternating current for driving a motor, and converts regenerative alternating current from the motor to the regenerative direct current. The regenerative direct current from the inverter circuit passes through the resistor. The regenerative direct current passes thorough the resistor upon the current detector detecting the regenerative current exceeding a predetermined value.Type: ApplicationFiled: September 27, 2023Publication date: April 4, 2024Inventors: Yuji IDE, Michio KITAHARA, Shunichi MIYAZAKI, Toshio HIRAIDE
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Patent number: 6570484Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: GrantFiled: September 13, 2002Date of Patent: May 27, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Publication number: 20030038705Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: ApplicationFiled: September 13, 2002Publication date: February 27, 2003Applicant: Murata Manufacturing Co., Ltd.Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Patent number: 6489880Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: GrantFiled: September 21, 2001Date of Patent: December 3, 2002Assignee: Murata Manufacturing Co., Ltd.Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Publication number: 20020011918Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: ApplicationFiled: September 21, 2001Publication date: January 31, 2002Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Patent number: 6148367Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.Type: GrantFiled: December 24, 1996Date of Patent: November 14, 2000Assignee: Hitachi, Ltd.Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
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Patent number: 6020809Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: GrantFiled: February 9, 1999Date of Patent: February 1, 2000Assignee: Murata Manufacturing Co., Ltd.Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Patent number: 5929743Abstract: A thermistor with positive resistance-to-temperature characteristic used in a overcurrent protection circuit has electrodes on mutually opposite main surfaces and is mounted to a substrate having electrically conductive members such that deterioration of its voltage resistance due to heat emission can be controlled. A spacer with smaller thermal conductivity than the substrate and penetrated by a conductor piece with a small cross-sectional area is inserted between solder materials connecting to one of the thermistor electrodes. The other electrode is contacted by an elongated connecting member through its sectional surface transverse to its longitudinal direction such that the cross-sectional area of electrical conduction is reduced.Type: GrantFiled: November 8, 1996Date of Patent: July 27, 1999Assignee: Murata Manufacturing Co., Ltd.Inventors: Michio Miyazaki, Haruyuki Takeuchi, Tadao Bekku
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Patent number: 5867083Abstract: A small-size high-performance electronic protective device (10) is provided for use in protecting communication equipment including an exchange servicing module against application of abnormal surge current due to accidental shorts between adjacent ones of power feed lines in a communications system. The protective device (10) includes positive thermistors (3a, 3b) connected between communication link input terminals (1a, 1b) and output terminals (1c, 1d) coupled to an associative equipment being protected. The protective device (10) also includes thick-film resistive elements (5a, 5b), which are connected in parallel with the thermistors (3a, 3b), respectively.Type: GrantFiled: June 28, 1996Date of Patent: February 2, 1999Assignee: Murata Manufacturing Co., Ltd.Inventors: Haruyuki Takeuchi, Michio Miyazaki, Tadao Bekku
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Patent number: 5623631Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.Type: GrantFiled: February 3, 1995Date of Patent: April 22, 1997Assignees: Hitachi, Ltd., Hitachi Microcomputer System, Ltd.Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
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Patent number: 5418929Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.Type: GrantFiled: January 28, 1994Date of Patent: May 23, 1995Assignee: Hitachi, Ltd.Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
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Patent number: 5353422Abstract: An information medium storage and management system includes storage compartments for storing a plurality of information media; a plurality of recording/reproducing apparatus each capable of accessing each of a plurality of information media, each capable of recording at least one file; handling apparatus for mounting a mount information medium on a mount recording/reproducing apparatus and demounting a demount information medium from a demount recording/reproducing apparatus; and a controller for controlling the handling apparatus to select as the mount information medium one of the plurality of information media in accordance with the use history data of each information medium, to select as the mount recording/reproducing apparatus one of unoccupied recording/reproducing apparatus of the plurality of recording/reproducing apparatus, and to cause the mount information medium to use the mount recording/reproducing apparatus for a predetermined time period.Type: GrantFiled: October 1, 1990Date of Patent: October 4, 1994Assignee: Hitachi, Ltd.Inventors: Takashi Kobayashi, Kenzo Kurihara, Takashi Doi, Michio Miyazaki, Minoru Kosuge
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Patent number: 5307473Abstract: In allocating an area of a cache memory to each storage unit, proper allocation of the cache memory is made to each storage unit. If the amount of write-after data becomes equal to or more than a threshold value, an allocation limit is set to each disk unit. If CPU issues a data write request requiring the amount of data equal to or more than the allocation limit, the data write request is held in a wait state until the amount of write-after data becomes less than the allocation limit. Therefore, the allocation amount to the disk unit becomes neither too large nor too small. In this manner, proper allocation of the cache memory to each disk unit can be realized.Type: GrantFiled: February 10, 1992Date of Patent: April 26, 1994Assignees: Hitachi, Ltd., Hitachi Microcomputer System Ltd.Inventors: Toshiaki Tsuboi, Akira Yamamoto, Shigeo Honma, Yoshihiro Asaka, Koji Ozawa, Hiroyuki Kitajima, Michio Miyazaki
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Patent number: 5267097Abstract: When a positioning operation of a head on a track of a disk including a target record is completed, information is read out from the track of the disk and stored in a buffer memory without waiting a read command from a host side controller. A transfer operation of the target record of the information from the buffer memory to the controller is performed when the controller is not busy and generates the read command. A transfer rate of the record from the buffer memory to the controller is made faster than a read rate of the information from a disk or a write rate into the buffer memory, so that a nominal transfer rate of an entire system is increased without changing the read or write rate.Type: GrantFiled: September 14, 1992Date of Patent: November 30, 1993Assignee: Hitachi, Ltd.Inventors: Akihito Ogino, Michio Miyazaki, Kiyoshi Hisano
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Patent number: 5257352Abstract: An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In response to an output request from a HOST system to the disc systems, data outputted from the latter are stored in the storage areas of the cache memory. The data stored in the storage areas and outputted therefrom in response to the output request are transferred to the disc systems. The storage areas storing the data requested and not yet stored in the disc systems are grouped correspondingly to the disc systems where the output data are to be stored. The resulting group is managed as a first attribute group. Write-after processing for every disc units can be executed in parallel efficiently without involving high processing overhead.Type: GrantFiled: July 5, 1990Date of Patent: October 26, 1993Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Akira Yamamoto, Toshiaki Tsuboi, Takao Sato, Yoshihiro Asaka, Shigeo Honma, Shigeru Kishiro, Michio Miyazaki, Yoshiaki Kuwahara, Hiroyuki Kitajima
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Patent number: 5187778Abstract: Buffers are separately provided for a region for non-sequential transfer and for a region for sequential transfer in each one of the disk units. A director sends a message to inform at least one of the disk units whether transfer of data the respective disk units are to make is sequential or non-sequential. When the disk unit receives a non-sequential transfer request, it uses the buffer region for non-sequential transfer to transfer data requested by the director and when it receives a sequential transfer request, it uses a plurality of buffer regions for the sequential transfer. Thus, data transfer is performed between a host device and that disk unit.Type: GrantFiled: September 10, 1990Date of Patent: February 16, 1993Assignee: Hitachi, Ltd.Inventors: Akira Yamamoto, Hiroyuki Kitajima, Akira Kurano, Michio Miyazaki, Masafumi Nozawa, Takikazu Takeuchi
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Patent number: 4833665Abstract: Method for controlling information recording in an information recording apparatus which includes a rewritable information record medium containing a data record area having a plurality of data recording blocks and an alternative area in which data to be written into a defective block in the data record area is written, and writing and reading of data to and from the blocks and erasing of data may be carried out, wherein, data is written into the respective blocks in the data record area on the information record medium, and if a data record error is detected, data to be written into the defect block is written into a block of the alternative area. When data is subsequently rewritten, contents of all blocks in the data record area to be rewritten, including the block previously determined to be defective, are erased and the new data is rewritten, and the content of the alternative area is erased.Type: GrantFiled: June 23, 1987Date of Patent: May 23, 1989Assignees: Hitachi, Ltd., Nippon T & TInventors: Kenji Tokumitsu, Takashi Doi, Michio Miyazaki, Yuji Yamane, Nobuyoshi Izawa, Toru Takeda
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Patent number: 4677606Abstract: A data recording/reproducing method for a non-rewritable recording medium of a rotating type, each of tracks on the recording medium is divided into a plurality of blocks which are allotted with respective addresses. Each block includes a data recording area and a deletion flag area which is divided into a plurality of sub-areas. One of the sub-areas in a given block is associated with other block which is in a predetermined address relation with the given block. When the content in the data recording area of one block on the recording medium is to be rendered invalid, deletion flag information is also recorded in the sub-area of the other block having the predetermined address relation with the one block. Upon reading, the data of the blocks read out from the recording medium exclusive of the data of the block determined to be invalid on the basis of the flag information is transferred to a high-rank system.Type: GrantFiled: August 15, 1984Date of Patent: June 30, 1987Assignee: Hitachi, Ltd.Inventors: Mikito Ogata, Masahito Mori, Takashi Doi, Michio Miyazaki
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Patent number: 4638472Abstract: An information recording method and system for writing information onto a recording medium. If an error area is detected in a check of the information read out of the medium after writing, the information is rewritten onto an alternative area on the recording medium using a buffer memory while the information in the error area is kept valid. Loss time accessing the alternative area is eliminated until the error checking and correction in the error checking and correction circuit is not available for the information read out of the error area through a reading circuit.Type: GrantFiled: March 9, 1984Date of Patent: January 20, 1987Assignee: Hitachi, Ltd.Inventors: Mikito Ogata, Masahito Mori, Takashi Doi, Michio Miyazaki, Takafumi Oka
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Patent number: 4611314Abstract: In an information storage system including a rotating recording medium having a number of information tracks, a head positioning mechanism for switching access position between adjacent tracks and a plurality of buffer memories each capable of storing one track of data, an alternate record area for storing data in substitution for an error data block is provided at an end of each of the tracks of the recording medium, and if an error data block is detected by a read-after-write check of the data during the rotation of the disc after the data has been written in one of the tracks from one of the buffer memories during the previous rotation of the disc, the data from the other buffer memory is written in the adjacent track or the data is read from the adjacent track and checked during a disc rotation waiting time required before the data write operation to the alternate record area is started.Type: GrantFiled: April 8, 1983Date of Patent: September 9, 1986Assignee: Hitachi, Ltd.Inventors: Mikito Ogata, Masahito Mori, Takashi Doi, Michio Miyazaki