Patents by Inventor Michio Murata
Michio Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10962565Abstract: There is provided a substrate inspection apparatus capable of inspecting the electrical characteristics of a packaged semiconductor device in a mounting environment. A prober includes a test box, a probe card and a package inspection card. A packaged device is attached to the package inspection card. A test board of the test box and a card board of the package inspection card reproduce the mounting environment in which a wafer-level system-level test is performed.Type: GrantFiled: February 7, 2017Date of Patent: March 30, 2021Assignee: TOKYO ELECTRON LIMITEDInventors: Michio Murata, Tatsuo Kawashima
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Publication number: 20190107557Abstract: There is provided a substrate inspection apparatus capable of inspecting the electrical characteristics of a packaged semiconductor device in a mounting environment. A prober includes a test box, a probe card and a package inspection card. A packaged device is attached to the package inspection card. A test board of the test box and a card board of the package inspection card reproduce the mounting environment in which a wafer-level system-level test is performed.Type: ApplicationFiled: February 7, 2017Publication date: April 11, 2019Inventors: Michio MURATA, Tatsuo KAWASHIMA
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Patent number: 10114070Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.Type: GrantFiled: September 16, 2014Date of Patent: October 30, 2018Assignee: TOKYO ELECTRON LIMITEDInventors: Michio Murata, Shingo Morita, Kenichi Narikawa
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Patent number: 9678107Abstract: There is provided a substrate inspection apparatus in which a contact between a probe and a semiconductor device is checked without using an IC tester. Further, when an abnormal state is detected in the contact check, a cause of the abnormal state can be determined. A prober includes a probe card having a plurality of probes to be contacted with respective electrode pads of the semiconductor device formed on a wafer W. The probe card includes a card-side inspection circuit configured to reproduce a circuit configuration of DRAM in which the semiconductor device cut from the wafer W is to be mounted, and a comparator configured to measure a potential of a line between the probe and the card-side inspection circuit.Type: GrantFiled: March 24, 2015Date of Patent: June 13, 2017Assignee: TOKYO ELECTRON LIMITEDInventors: Shingo Morita, Michio Murata
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Patent number: 9246308Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width smaller than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.Type: GrantFiled: May 30, 2014Date of Patent: January 26, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Jun-ichi Hashimoto, Michio Murata
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Patent number: 9240675Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width larger than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.Type: GrantFiled: May 30, 2014Date of Patent: January 19, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Jun-ichi Hashimoto, Michio Murata
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Publication number: 20150276810Abstract: There is provided a substrate inspection apparatus in which a contact between a probe and a semiconductor device is checked without using an IC tester. Further, when an abnormal state is detected in the contact check, a cause of the abnormal state can be determined. A prober includes a probe card having a plurality of probes to be contacted with respective electrode pads of the semiconductor device formed on a wafer W. The probe card includes a card-side inspection circuit configured to reproduce a circuit configuration of DRAM in which the semiconductor device cut from the wafer W is to be mounted, and a comparator configured to measure a potential of a line between the probe and the card-side inspection circuit.Type: ApplicationFiled: March 24, 2015Publication date: October 1, 2015Inventors: Shingo MORITA, Michio MURATA
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Publication number: 20150077152Abstract: A substrate inspection apparatus can efficiently inspect electric characteristics of the semiconductor device. A prober 10 includes a probe card 15 having a multiple number of probe needles 17 to be brought into contact with electrodes of a semiconductor device formed on a wafer W; and a test box 14 electrically connected to the probe card 15. A card-side inspection circuit of the probe card 15 reproduces a circuit configuration on which the semiconductor device is to be mounted after separated from the wafer W, e.g., the circuit configuration of a function extension card, and a box-side inspection circuit 21 of the test box 14 reproduces a circuit configuration on which the semiconductor device is to be mounted, e.g., a part of the circuit configuration of the mother board.Type: ApplicationFiled: September 16, 2014Publication date: March 19, 2015Inventors: Michio Murata, Shingo Morita, Kenichi Narikawa
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Publication number: 20140355637Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width larger than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.Type: ApplicationFiled: May 30, 2014Publication date: December 4, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Jun-ichi HASHIMOTO, Michio MURATA
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Publication number: 20140355634Abstract: A quantum cascade laser includes a semiconductor substrate including a principal surface; a mesa waveguide disposed on the principal surface of the semiconductor substrate, the mesa waveguide including a light emitting region and an upper cladding layer disposed on the light emitting region, the mesa waveguide extending in a direction orthogonal to a reference direction; and a current blocking layer formed on a side surface of the mesa waveguide. The light emitting region includes a plurality of core regions and a plurality of buried regions. The core regions and the buried regions are alternately arranged in the reference direction. The core region at a central portion of the mesa waveguide has a width smaller than a width of the core region at a peripheral portion of the mesa waveguide in the reference direction.Type: ApplicationFiled: May 30, 2014Publication date: December 4, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Jun-ichi HASHIMOTO, Michio MURATA
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Publication number: 20140348196Abstract: A semiconductor optical device assembly includes a quantum cascade laser including first to fifth portions; and a sub-mount having a mount surface including first to third areas, the first area and the third area supporting the first portion and the fifth portion of the quantum cascade laser. The quantum cascade laser includes a substrate having a main surface; a semiconductor mesa disposed on the main surface in the third portion, the semiconductor mesa including a light emitting layer; and an electrode disposed on a surface in the first to fifth portions of quantum cascade laser, the electrode being in contact with an upper surface of the semiconductor mesa. The quantum cascade laser is mounted on the sub-mount with a gap formed between a surface of the electrode of the third portion of the quantum cascade laser and the second area of the sub-mount.Type: ApplicationFiled: May 21, 2014Publication date: November 27, 2014Inventors: Hiroyuki Yoshinaga, Michio Murata
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Patent number: 8804785Abstract: A quantum cascade semiconductor laser includes a n-type semiconductor substrate, the substrate having a main surface; a mesa waveguide disposed on the substrate, the mesa waveguide including a core layer and an n-type upper cladding layer disposed on the core layer; a first semiconductor layer disposed on a side surface of the mesa waveguide and the main surface of the substrate, the first semiconductor layer being in contact with the side surface of the mesa waveguide; and a second semiconductor layer disposed on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer constitute a burying region embedding the side surfaces of the mesa waveguide. The first semiconductor layer is formed of at least one of a semi-insulating semiconductor and a p-type semiconductor. In addition, the second semiconductor layer is formed of an n-type semiconductor.Type: GrantFiled: May 31, 2013Date of Patent: August 12, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Jun-ichi Hashimoto, Takashi Kato, Hiroshi Inada, Michio Murata
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Publication number: 20130329761Abstract: A quantum cascade semiconductor laser includes a n-type semiconductor substrate, the substrate having a main surface; a mesa waveguide disposed on the substrate, the mesa waveguide including a core layer and an n-type upper cladding layer disposed on the core layer; a first semiconductor layer disposed on a side surface of the mesa waveguide and the main surface of the substrate, the first semiconductor layer being in contact with the side surface of the mesa waveguide; and a second semiconductor layer disposed on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer constitute a burying region embedding the side surfaces of the mesa waveguide. The first semiconductor layer is formed of at least one of a semi-insulating semiconductor and a p-type semiconductor. In addition, the second semiconductor layer is formed of an n-type semiconductor.Type: ApplicationFiled: May 31, 2013Publication date: December 12, 2013Inventors: Jun-ichi HASHIMOTO, Takashi KATO, Hiroshi INADA, Michio MURATA
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Patent number: 8300992Abstract: A semiconductor optical modulator with the Mach-Zender type is disclosed. The optical modulator of the invention cab driven by a single phase signal and reduce the chirping of the modulated light. Two waveguides of the Mach-Zender modulator each including an active layer showing the exciton resonance in the refractive index are connected with a resistor. The driving signal is applied to one of the waveguides, while, the signal is applied to the other waveguide through the resistor where the other waveguide is grounded through a resistor. Adjusting the resistance of two resistors and the amplitude of the applied signal, the Mach-Zender modulator shows a substantial modulation degree with substantially no chirping characteristic.Type: GrantFiled: September 21, 2010Date of Patent: October 30, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata
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Patent number: 8243768Abstract: A semiconductor diffraction grating device includes a semiconductor substrate having a principal surface, a semiconductor core layer and a semiconductor cladding layer provided on the principal surface, and a chirped grating structure provided between the semiconductor core layer and the semiconductor cladding layer. The chirped grating structure includes a first region, a second region, and a third region arranged in that order in a predetermined axis direction, the first, second, and third regions including a plurality of projections constituting a chirped grating. The plurality of projections are provided at placement positions arranged with a predetermined pitch in the predetermined axis direction. The coupling coefficient ? of the chirped grating monotonically increases in the predetermined axis direction to a predetermined value in the first region, remains flat in the second region, and monotonically decreases in the predetermined axis direction from the predetermined value in the third region.Type: GrantFiled: October 12, 2010Date of Patent: August 14, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata
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Patent number: 8063408Abstract: In an integrated semiconductor optical device, a first cladding layer is made of a first conductivity type semiconductor. A first active layer for forming a first semiconductor optical device is provided on the first cladding layer in a first area of a principal surface of a substrate. A second active layer for forming a second semiconductor optical device is provided on the first cladding layer in a second area of the principal surface. A second cladding layer made of a second conductivity type semiconductor is provided on the second active layer. A third cladding layer made of a first conductivity type semiconductor is provided on the first active layer. A tunnel junction region is provided between the first active layer and the third cladding layer. The first active layer is coupled to the second active layer by butt joint. The second and third cladding layers form a p-n junction.Type: GrantFiled: October 28, 2009Date of Patent: November 22, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata
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Patent number: 8003995Abstract: A semiconductor optical device where the leak current due to the double injection of carriers may be suppressed and a simplified process to form the device are disclosed. The device 10 provides, on the n-type InP substrate, a mesa and a burying region formed so as to bury the mesa. The mesa includes the first cladding layer, the active layer, the tunnel junction layer and the second cladding layer on the n-type InP substrate in this order. The tunnel junction layer comprises an n-type layer coming in contact with the active layer and a p-type layer between the active layer and the n-type layer. The n-type layer has a carrier concentration higher than that of the second cladding layer, while, the p-type layer may have the band gap energy greater than that of the second cladding layer.Type: GrantFiled: August 25, 2008Date of Patent: August 23, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata
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Publication number: 20110090931Abstract: A semiconductor diffraction grating device includes a semiconductor substrate having a principal surface, a semiconductor core layer and a semiconductor cladding layer provided on the principal surface, and a chirped grating structure provided between the semiconductor core layer and the semiconductor cladding layer. The chirped grating structure includes a first region, a second region, and a third region arranged in that order in a predetermined axis direction, the first, second, and third regions including a plurality of projections constituting a chirped grating. The plurality of projections are provided at placement positions arranged with a predetermined pitch in the predetermined axis direction. The coupling coefficient ? of the chirped grating monotonically increases in the predetermined axis direction to a predetermined value in the first region, remains flat in the second region, and monotonically decreases in the predetermined axis direction from the predetermined value in the third region.Type: ApplicationFiled: October 12, 2010Publication date: April 21, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES. LTD.Inventor: Michio MURATA
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Publication number: 20110069924Abstract: A semiconductor optical modulator with the Mach-Zender type is disclosed. The optical modulator of the invention cab driven by a single phase signal and reduce the chirping of the modulated light. Two waveguides of the Mach-Zender modulator each including an active layer showing the exciton resonance in the refractive index are connected with a resistor. The driving signal is applied to one of the waveguides, while, the signal is applied to the other waveguide through the resistor where the other waveguide is grounded through a resistor. Adjusting the resistance of two resistors and the amplitude of the applied signal, the Mach-Zender modulator shows a substantial modulation degree with substantially no chirping characteristic.Type: ApplicationFiled: September 21, 2010Publication date: March 24, 2011Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Michio MURATA
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Patent number: 7803645Abstract: The present invention is to provide a light-emitting device, a laser diode, formed without using the mechanical cleavage, and a process for manufacturing the device. The process comprises, after stacking semiconductor layers of the first cladding layer, the active layer, and the second cladding layer, a forming of a groove to define the laser resonator, the depth of which reaches the substrate, and the mass-transportation, within the groove, from the side surface of the groove in a portion of the substrate and the first cladding layer to the facet of the active layer and the second cladding layer. Since the facet layer thus transported reflects the crystal orientation of the side of the groove, the crystal quality of the facet layer can be maintained.Type: GrantFiled: February 27, 2006Date of Patent: September 28, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventor: Michio Murata