Patents by Inventor Michio Murooka

Michio Murooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5431773
    Abstract: A method of manufacturing a semiconductor device, which comprises steps of providing a substrate, forming an oxide layer of a metal material, which includes a tantalum or an alloy mainly containing a tantalum on the substrate, placing the substrate into a first chamber, activating an etching gas which includes a fluorine containing gas and an oxygen containing gas, in a second chamber, introducing the activated etching gas into the second chamber, and etching the oxide layer by the introduced gas selectively against the substrate.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: July 11, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsushi Ikeda, Michio Murooka
  • Patent number: 5428250
    Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta--Mo alloy, a Ta--Nb alloy, a Ta--W alloy, a TaN alloy, a Ta--Mo--N alloy, a Ta--Nb--N alloy and a Ta--W--N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.
    Type: Grant
    Filed: July 22, 1993
    Date of Patent: June 27, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsushi Ikeda, Michio Murooka
  • Patent number: 5296653
    Abstract: A multi-layered conductor structure device has a substrate, a first conductor layer formed on the substrate, which provides an electrode or wiring, and an insulating film covering the first conductor layer and the substrate. On the insulating film, a second conductor layer is formed which comprises an indium tin oxide, and which provides an electrode or wiring. The first conductor layer is formed of an alloy of aluminum with copper, gold, boron, bismuth, cobalt, chromium, germanium, iron, molybdenum, niobium, nickel, palladium, platinum, tantalum, titanium, tungsten, and/or silver.
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: March 22, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kiyota, Mitsushi Ikeda, Meiko Ogawa, Yoshifumi Ogawa, Michio Murooka
  • Patent number: 5264728
    Abstract: The line material is of a laminated structure consisting of: a Ta containing N alloy layer (lower layer) which is a first metal layer made of at least an alloy selected from the group consisting of a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; a second metal layer (upper layer) formed integrally with the first metal layer and made of at least an alloy selected from the group consisting of Ta, a Ta-Mo alloy, a Ta-Nb alloy, a Ta-W alloy, a TaN alloy, a Ta-Mo-N alloy, a Ta-Nb-N alloy and a Ta-W-N alloy; and/or a pin hole-free oxide film. The line material of the laminated structure is to be applied to the formation of signal lines and electrodes of, e.g., a liquid crystal display. The line material has a low resistance and the insulating film formed by anodization and the like exhibits excellent insulation and thermal stability. Therefore, when the line material is applied to signal lines of various devices, it exhibits excellent characteristics.
    Type: Grant
    Filed: November 30, 1990
    Date of Patent: November 23, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsushi Ikeda, Michio Murooka
  • Patent number: 5187602
    Abstract: An object is to provide an active matrix type liquid crystal display apparatus with a substrate for a liquid crystal driving semiconductor device which is free from point defects, rise of production costs, and shortcircuit in a storage capacitance portion. The liquid crystal display apparatus has a substrate for a liquid crystal driving semiconductor device with a display picture element group consisting of driving semiconductor devices 15 and storage capacitances, the display picture element group being disposed on one major surface of a transparent substrate 13, wherein the storage capacitance is formed by disposing an anodic oxide film 18 between a display electrode 16 and a storage capacitance metallic line 1b made of TaN, for example, and disposed on the one major surface of the transparent substrate 13.
    Type: Grant
    Filed: July 10, 1991
    Date of Patent: February 16, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsushi Ikeda, Michio Murooka