Abstract: According to one embodiment, a voltage generation circuit includes: a charge pump circuit configured to boost a voltage input to a first node and output a first signal to a second node; an operational amplifier configured to receive a first reference voltage and a first voltage obtained by dividing a voltage of the second node and output a second signal to a third node; a first transistor having a gate coupled to the third node, one terminal coupled to a power supply, and the other terminal coupled to the first node; a logic circuit configured to detect the voltage of the second node and output a third signal; and a charge-up circuit configured to receive the third signal and charge a voltage of the third node.

Abstract: According to one embodiment, a voltage generation circuit includes: a charge pump circuit configured to boost a voltage input to a first node and output a first signal to a second node; an operational amplifier configured to receive a first reference voltage and a first voltage obtained by dividing a voltage of the second node and output a second signal to a third node; a first transistor having a gate coupled to the third node, one terminal coupled to a power supply, and the other terminal coupled to the first node; a logic circuit configured to detect the voltage of the second node and output a third signal; and a charge-up circuit configured to receive the third signal and charge a voltage of the third node.

Abstract: A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.

Abstract: A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals.

Abstract: A nonvolatile semiconductor memory device includes a memory cell group, transfer transistor, and switching circuit. The memory cell group has a plurality of memory cells each including a floating gate and control gate, and the current paths of the plurality of memory cells are connected in series. The transfer transistor transfers a write voltage to at least one memory cell in the memory cell group. The switching circuit applies a voltage to the gate of the transfer transistor. In a write operation, when a first voltage higher than a power supply voltage and lower than the write voltage is applied to the control gate of an unselected memory cell, the switching circuit applies an intermediate voltage higher than the first voltage and equal to or lower than the write voltage to the gate of the transfer transistor.

Abstract: A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.

Abstract: A multi-level programmable nonvolatile semiconductor memory device comprises, a charge accumulation layer, a control gate which bias a potential to the charge accumulation layer, wherein the potential of the charge accumulation layer is controlled discretely according to the number of electrons accumulated in the charge accumulation layer.

Abstract: A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals.

Abstract: A nonvolatile semiconductor memory device includes a plurality of electronically reprogrammable memory cells, a circuit for applying a plurality of pulse signals having corresponding high level potentials increasing step by step to said memory cell, and verify circuit for detecting a threshold value of said memory cell after applying said plurality of pulse signals.

Abstract: To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.

Abstract: A non volatile semiconductor memory device wherein it is possible to transfer Vpp without a drop in voltage of the transfer transistor Vth (threshold voltage) in a transfer circuit or decoder circuit for selectively transferring Vpp by using a usual LVP (low voltage P type transistor) to reduce step(s) of production process and costs. An LVP (low voltage P type transistor) instead of a HVP (high voltage P type transistor) for a transfer circuit is used. Two-way diodes each of which threshold value becomes about Vdd are inserted between the gate and the drain.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A multi-level programmable nonvolatile semiconductor memory device comprises, a charge accumulation layer, a control gate which bias a potential to the charge accumulation layer, wherein the potential of the charge accumulation layer is controlled discretely according to the number of electrons accumulated in the charge accumulation layer.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

Abstract: A submerged motor pump is provided in a piping system or connected to a pressure vessel, and a pump and a motor are immersed in the fluid. A rotor rotatable together with a pump impeller is fixed to a rotor shaft. The rotor shaft is supported by a thrust bearing. A cover is provided facing the end of the rotor shaft and carries an ultrasonic sensor on its outside surface. The ultrasonic sensor projects ultrasonic wave toward the end of the rotor shaft and detects the echo therefrom so as to measure the distance between the end of the rotor shaft and the inside surface of the cover, i.e. the surface thereof in contact with the fluid. The inside surface of the cover includes a concave spherical surface which faces the end of the rotor shaft and substantially converges the main beam of the ultrasonic wave to the end of the rotor shaft, preventing reduction of sound pressure of the ultrasonic wave.

Abstract: An electroosmotic dewaterer for dehydrating a liquid mud by supplying the liquid mud into a space between facing anode and cathode electrodes, applying d.c. voltage across said electrodes so as to gather the water content of the liquid mud to the cathode electrode by means of electroosmotic action and filtering the liquid through a filtering medium, wherein the cathode electrode is equipped with means for removing a deposit formed on the surface thereof while the dehydrating operation is carried out.

Abstract: An aseismatic device for a door comprises a main portion and a roller-bearing plate. The main portion includes a plate capable of being attached to one upper corner of one side door, which is to be closed and locked. The plate is provided with a longitudinally rotatable roller in such a manner that it projects somewhat upwardly and with a laterally rotatable roller in such a manner that it projects somewhat laterally.The roller-bearing plate is capable of being attached to one corner portion of a door frame corresponding to said main portion, and has a pair of planes for bearing said rollers.The main portion and the roller-bearing plate are arranged in such a manner that the rollers are normally not in contact with said bearing planes.